TECHNICAL PROGRAM 2016
2016 PLENARY SESSION
Challenges and Opportunities in Nano-Scale CMOS Design
Dr. Kevin X. Zhang, Fellow and Vice President, Technology & Manufacturing Group, Intel
Kevin Zhang is a Vice President of Technology and Manufacturing Group and an Intel Fellow at Intel Corporation. He is responsible for advanced circuit technology development for the company’s future products. Dr. Zhang oversees the development of process design rules, circuit & device modeling, digital circuit libraries, key analog and mixed-signal circuits, high-speed I/O and embedded memories. Zhang has published more than 60 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds more than 50 U.S. patents in the field of integrated circuit technology. Zhang is 2016 ISSCC Program chair and also serves on IEEE VLSI Executive Committee. Zhang is a Fellow of the Institute of Electrical and Electronics Engineers. He received his bachelor’s degree from Tsinghua University in Beijing in 1987 and his Ph.D. from Duke University in 1994, both in electrical engineering.
Semi Consolidation in an Age of Moore Anxiety
Joe Sawicki, Vice President and GM, Design-to-Silicon, Mentor Graphics
Joseph Sawicki is the Vice-President and General Manager of the Design-to-Silicon division at Mentor Graphics. An expert in IC nanometer design and manufacturing challenges, Sawicki is responsible for Mentor’s industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform, and the Tessent design-for-test product line. Sawicki joined Mentor Graphics in 1990, and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University’s High Technology Program, and has completed the Harvard Business School Advanced Management Program.
INVITED SPEAKERS
Design for Stress for CMOS Technologies – The next frontier, Riko Radojcic, Consultant
On the Electrical Performance of Rigid Silicon Interposer, Farhang Yazdani, BroadPak Corp.
BEOL Process Integration for the 7nm Technology Node, Theodorus Standaert, IBM
Materials Science of Ru and Ru Alloy Thin Films for Barrier Applications, John Ekerdt, UT Austin
Process options to enable (sub-)1e-9 Ohm.cm2 contact resistivity on Si devices, Steven Demuynck, imec
Fabrication of nanotwinned Cu and its applications in interconnects of microelectronic devices, Chih Chen, National Chiao-Tung University
3D architecture and interconnect for emerging memory technologies, Dr. Er-Xuan Ping, AMAT
Superconducting Circuits for Quantum Information, R.J. Schoelkopf, Yale University
Interconnects for beyond CMOS devices, Iuliana Radu, imec
Technology and Design Architectures and Process Innovations for 7 and 5nm BEOL Interconnects, Larry Clevenger, IBM
Scaling of Interconnect Reliability, Anthony Oates, TSMC
Advanced analytical methods for mechanical and structural characterization of nanoscale materials for 3D IC integration, Ehrenfried Zschech, Fraunhofer Institute for Ceramic Technologies and Systems IKTS, Dresden, Germany
Monday, May 23
Workshop
(see separate tab)
Tuesday, May 24
SESSION 1: Plenary Session
8:15 – 9:15
Welcome
Jon Candaleria (Chair) NA 2016 IITC/AMC Conference
Keynote Presentation
Semi Consolidation in an Age of Moore Anxiety,
Joe Sawicki, Vice President and GM, Design-to-Silicon, Mentor Graphics
SESSION 2: Process Integration
9:25 – 10:45
2.1 INVITED -BEOL Process Integration for the 7 nm Technology Node, T. Standaert, G. Beique*, H.-C. Chen, S.-T. Chen, B. Hamieh, J. Lee, P. McLaughlin, J. McMahon*, Y. Mignot, F. Mont*, K. Motoyama, S. Nguyen, R. Patlolla, B. Peethala, D. Priyadarshini, M. Rizzolo, N. Saulnier, H. Shobha, S. Siddiqui*, T. Spooner, H. Tang, O. van der Straten, E. Verduijn*, Y. Xu, X. Zhang*, J. Arnold, D. Canaperi, M. Colburn, D. Edelstein, V. Paruchuri, G. Bonilla, IBM, *GLOBALFOUNDRIES
2.2 Performance Enhancement for 14nm High Volume Manufacturing Microprocessor and System on a Chip Processes, K.Fischer, H.K Chang, D.Ingerly, I.Jin, H. Kilambi, J. Longun, R.Patel, C.Pelto, C. Petersburg, P.Plekhanov, C.Puls, L. Rockford, I. Tsameret, M.Uncuer, P.Yashar, Intel Corporation
2.3 450mm Cu Single Damascene BEOL Process with 20nm Half-Pitched Features, Sunoo Kim, Shannon Dunn, Steven Smith, WenLi Collision, Jamie Prudhomme, Huey-Ming Wang, Joe Maniscalco, Nithin Yathapu, Chulgi Song, Barry Wang, Christopher Carr, Hsi-Wen Liu, Bruce Gall, Angelo Alaestante, Min-Hui Chen, Richard Conti, ChungJu Yang, Denis Sullivan, Kosta Culafi, BumKi Moon, Yii-Cheng Lin, Yu-Lieh Fu, Katherine Sieg, Anne-Sophie Larrea, Norman Fish, Regina Swaine, Alexander Bialy, Milo Tallon, Gerard Stapf, John Hagwood, Michael Bryant, Rand Cottle, Stock Chang, Mark Kelling, Karsten Schaefer ,Dan Franca, Pinyen Lin, Christopher Borst, Kwangwook Lee, JongHeun Lim, David Skilbred, CC Chien, Frank Robertson, Erin Fria, Global 450mm Consortium (G450C)
SESSION 3: Process Integration (continued)
11:00 – 12:20
3.1 INVITED – Technology and Design Architectures and Process Innovations for 7 and 5nm BEOL Interconnects, Larry Clevenger, IBM Research
3.2 Interconnect Performance and Scaling Strategy at the 5 nm Node, James Hsueh-Chung Chen, Nicholas LiCausi*, E. Todd Ryan*, Theodorus E Standaert, Griselda Bonilla, IBM Research, *GlobalFoundries
3.3 10nm Local Interconnect Challenge with Iso-dense Loading and Improvement with ALD Spacer Process, Ming He, Christopher Ordonio, Chun Hui Low, Peter Welti, Granger Lobb, Aleksandra Clancy, Jeff Shu, Ayman Hamouda, Jason Stephens, Ketan Shah, Ashwini Chandrasekhar, Mary Claire Silvestre, Prakash Periasamy, Anbu Selvam KM Mahalingam, Shyam Pal and Craig Child, Globalfoundries
SESSION 4: MUP-ILD I
1:30 – 2:45
4.1 Ordered Porosity for Interconnect Applications, Jessica M Torres, Jeff Bielefeld, James Blackwell, David J Michalak and James Clarke Intel Corporation
4.2 Toward successful integration of gap-filling ultralow-k dielectrics, L. Zhang*, J.-F. de Marneffe, A. Leśniewska, P. Verdonck, N. Heylen, G. Murdoch, K. Croes, Zs. Tőkei, J. Bömmels, S. Lefferts**, S. De Gendt* and M.R. Baklanov, , imec, *KU Leuven, **SBA Materials
4.3 Physical Vapor Deposited AlN as Scalable and Reliable Interconnect Etch-Stop ≤ 10nm Node, He Ren, Yana Cheng, Yong Cao, Srinivas Guggilla, Sree Kesapragada, Weifeng Ye and Mehul Naik, Applied Materials Inc.
SESSION 5: MUP-Metal I
3:00 – 5:35
5.1 INVITED – Fabrication of (111) nanotwinned Cu and its applications in interconnects of microelectronic devices, Chih Chen, Chien-Min Liu, Tien-Lin Lu, Han-wen Lin, Yi-Cheng Chu, Chia-Ling Lu, Jing-Ye Juang*, Kuan-Neng Chen* and K. N. Tu**, National Chiao Tung University, *Industrial Technology Research Institute, **University of California at Los Angeles
5.2 Barrier/Liner Stacks for Scaling the Cu Interconnect Metallization, Marleen van der Veen, Nicolas Jourdan, Victor Vega Gonzalez, Chris Wilson, Nancy Heylen, Olalla Varela Pedreira, Herbert Struyf, Kristof Croes, Jürgen Bömmels and Zsolt Tőkei, imec
5.3 Ruthenium Interconnect Resistivity and Reliability at 48 nm pitch, Xunyuan Zhang, Huai Huang*, Raghuveer Patlolla*, Wei Wang*, Frank W. Mont, Juntao Li*, Chao-Kun Hu*, Eric G. Liniger*, Paul S. McLaughlin*, Cathy Labelle, E. Todd Ryan, Donald Canaperi*, Terry Spooner*, Griselda Bonilla*, Daniel Edelstein*, GLOBALFOUNDRIES, *IBM in Albany Nano Science & Technology Research Center
5.4 Ruthenium Metallization for Advanced Interconnects, Liang Gong Wen, Christoph Adelmann, Olalla Varela Pedreira, Shibesh Dutta, Mihaela Popovici, Basoene Briggs, Nancy Heylen, Kris Vanstreels, Christopher Wilson, Sven Van Elshocht, Kristof Croes, Jurgen Bommels and Zsolt Tokei, imec
5.5 CVD-Mn/CVD-Ru-based Barrier/Liner Solution for Advanced BEOL Cu/Low-k Interconnects, Nicolas Jourdan, Marleen Van der ween, Victor Vega Gonzalez, Kristof Croes, Alicja Lesniewska, Olalla Varela Pedreira, Sven Van Elshocht, Juergen Boemmels and Zsolt Tökei, imec
5.6 Experimental Study of Nanoscale Co Damascene BEOL Interconnect Structures, J. Kelly, J. H.-C. Chen, H. Huang, C. K. Hu, E. Liniger, R. Patlolla, B. Peethala, P. Adusumilli, H. Shobha, T. Nogami, T. Spooner, E. Huang, D. Edelstein, D. Canaperi, V. Kamineni* F. Mont*and S. Siddiqui* IBM, *GLOBALFOUNDRIES
Wednesday, May 25
SESSION 6: Plenary Presentation
8:15 – 9:05
Challenges and Opportunities in Nano-Scale CMOS Design,
Dr. Kevin X. Zhang, Fellow and Vice President, Technology & Manufacturing Group, Intel
SESSION 7: Novel System
9:15 – 10:35
7.1 INVITED – Superconducting Circuits for Quantum Information, R.J. Schoelkopf, Yale University
7.2 Modeling of Graphene for Interconnect Applications, Antonino Contino, Ivan Ciofi*, Maria Politou, Diederik Verkest*, Dan Mocuta*, Bart Sorée* and Guido Groeseneken*, KU Leuven, *Imec
7.3 Nanocarbon Interconnects Combining Vertical CNT Interconnects and Horizontal Graphene Lines, Raphael Ramos, Adeline Fournier, Murielle Fayolle-Lecocq and Jean Dijon, CEA Grenoble, University of Grenoble Alpes
SESSION 8: Novel Systems (continued)
10:50 – 12:10
8.1 INVITED – Interconnects for beyond CMOS devices, Iuliana Radu, imec
8.2 Performance Modeling and Optimization for On-Chip Interconnects in STT-MRAM Memory Arrays, Javaneh Mohseni, Chenyun Pan and Azad Naeemi, Georgia Institute of Technology
8.3 Performance Analyses and Benchmarking for Spintronic Devices and Interconnects, Chenyun Pan, Sou-Chi Chang and Azad Naeemi, Georgia Institute of Technology
SESSION 9: Reliability I
1:20 – 2:40
9.1 INVITED – Interconnect Reliability Challenges for Technology Scaling: A Circuit Focus, Anthony S. Oates, TSMC
9.2 A New Model for TDDB Reliability of Porous Low-K Dielectrics: Percolation Defect Nucleation and Growth, Shou-Chung Lee and A. S. Oates, TSMC
9.3 Resistance and Electromigration Performance of 6 nm Wires, Jasmeet Chawla, Seung Hoon Sung, Stephanie Bojarski, Colin Carver, Manish Chandhok, Ramanan Chebiam, James Clarke, Michael Harmes, Christopher Jezewski, Mauro Kobrinski, Brian Krist, Mona Mayeh, Robert Turkot and Hui Jae Yoo, Intel Corporation
SESSION 10: Contact and Silicide
2:55 – 4:15
10.1 INVITED – Process Options to Enable (Sub-)1e-9 Ohm.cm2 Contact Resistivity on Si Devices, H. Yu,, M. Schaekers, S. Demuynck, E. Rosseel, J. Everaert, S. A. Chew, A. Peter, S. Kubicek, K. Barla, A. Mocuta, N. Horiguchi, N. Collaert, A. V. –Y. Thean, K. De Meyer, imec
10.2 Towards contact integration for III-V/Silicon heterogeneous Photonics devices, Elodie Ghegin, Philippe Rodriguez*, Fabrice Nemouchi*, Christophe Jany*, Melisa Brihoum*, Aomar Halimaoui, Isabelle Sagnes** and Bertrand Szelag*, STMicroelectronics, *CEA-LETI and **CNRS-LPN
10.3 Contacts for Monolithic 3D architecture: Study of Ni0.9Co0.1 Silicide Formation, Philippe Rodriguez, Sylvie Favier*, Fabrice Nemouchi, Coralie Sésé, Fabien Deprat, Claire Fenouillet-Béranger and Patrice Gergaud, CEA LETI, *STMicroelectronics
SESSION 11: Poster Session
4:15 – 5:45
P-1 Towards the realization of optical interconnets on Si interposer, S. Killge, S. Charania, K. Richter, J. W. Bartha; Technische Universität Dresden
P-2 3D Die Level Packaging for Hybrid Systems, P.Vamsi Krishna Nittala, Prosenjit Sen, Indian Institute of Science
P-3 Photodetector of ZnO nanowires based on through-silicon via approach, Y.H. Chen,I.T. Huang, S.J. Chang, and T.J. Hsueh*, National Cheng Kung University, *National Nano Device Laboratories
P-4 Novel top-down Cu filling of through silicon via (TSV) in 3-D integration, T. C. Weng, J. L. Lu, S. J. Chang, T. J. Hsueh*, National Cheng Kung University, *National Nano Device Laboratories
P-5 Thermo-mechanical behavior of copper TSV and the effect of alternative metal liners, J. Shin, M. Thorum, J. Richardson, Lam Research Corporation
P-6 Impact of Across-Wafer Variation on the Electrical Performance of TSVs, L. Filipovic, S. Selberherr, A. P. Singulani*, F. Roger*, S. Carniello*, TU Wien, *ams AG
P-7 First Integration of NiCo on pMOS Transistors, F. Deprat, F. Nemouchi, C. Fenouillet-Beranger, M. Cassé, Ph. Rodriguez, B. Previtali, N. Rambal1, V. Delaye, M. Haond*, M. Mellier*, M. Gregoire*, M. Danielou, S. Favier*, P. Batude, M. Vinet, CEA Leti,*ST Microelectronics
P-8 Formation and stability of intermetallics formed by solid-state reaction of Ni on In0.53Ga0.47As, S. Zhiou, Ph. Rodriguez, F. Nemouchi, P. Gergaud, T. Nguyen-Thanh*, L. Rapenne**, CEA-Leti, *Inst. Neel, **Grenoble INP-LMGP
P-9 Formation and Microstructure of Thin Ti Silicide Films for Advanced Technologies, P. Adusumilli, A.S. Ozcan, C. Lavoie, J. Jordan-Sweet, N. Breil*, M. Raymond**, S. Polvino*, D. Prater, D. Deniz**, A.V. Carr, V. Kamineni**, IBM Research, *IBM Systems, **GLOBALFOUNDRIES
P-10 A Novel Analytical Capacitance Model for Sub-10 nm Interconnects, Indira Seshadri, Huai Huang, Pranita Kerber, James Chen, Larry Clevenger, IBM Corporation
P-11 Geometry impact on the reduction of Cu interconnect wire resistance, Wei Wang, Terry Spooner, Chih-Chao Yang, XunYuan Zhang*, IBM in Albany Nano Science & Technology Research Center, * GLOBALFOUNDRIES Inc.
P-12 The Cu Exposure Effect in AIO Etch at Advanced CMOS Technologies, Junqing Zhou, Qiyang He, Minda Hu, Kefang Yuan, Yibin Cao, Linlin Sun, Xinghua Song, Haiyang Zhang, Semiconductor Manufacturing International Corp.
P-13 Transforming the P4 Process to Enhance Mechanical and Fracture Properties of ULKs, S. Isaacson, C. Wang, K. Lionti**, W. Volksen**, T. Magbitang**, R. Dauskardt, and G. Dubois, Stanford University, *IBM Almaden Research Center
P-14 Post Porosity Plasma Protection Integration at 48 nm Pitch, Huai Huang, Krystelle Lionti*, Willi Volksen*, Terry Spooner, Hosadurga Shobha, Joe Lee, James Hsueh-Chung Chen, Teddie Magbitang*, Brown Peethala, Eric G Liniger**, Chao Kun Hu3, Elbert Huang, Donald F Canaperi, Theodorus E Standaert, Daniel C. Edelstein**, Alfred Grill**, Geraud Dubois*, Griselda Bonilla
IBM Research at Albany Nanotech, *IBM Almaden Research Center, **IBM T.J. Watson Research Center
P-15 Laser anneal of oxycarbosilane low-k film, M. Redzheb, S. Armini, K. Vanstreels, J. Meersschaut, M.R. Baklanov, Y. Wang*, S. Chen*, V. Le*, M. Awdshiew*, P. Van Der Voort**, imec, *Ultratech, Inc., **Ghent University
P-16 Reduced Damage for BEOL Integration of Ultra Low-k (uLK) Dielectric Materials, Andy Wills, Meisam Movassat, Hash Pakbaz and Nigel Hacker, SBA Materials
P-17 Amorphous Co-Ti alloy as a single layer barrier for Co local interconnect structure, Maryamsadat Hosseini, Junichi Koike, Yuji Sutou*, Larry Zhao, Steven Lai*, Reza Arghavani*, Tohoku University, *Lam Research
P-18 The Oxygen Barrier Properties of CoxMoy Diffusion Barrier for Cu Interconnect, Li-Ao Cao, Xin-Ping Qu, Fudan University
P-19 A Study on the Plating and Wetting Ability of Ruthenium-Tungsten Multi-layers for Advanced Cu Metallization, Tai-Chen Kuo, Yin-Hsien Su, Wen-Hsi Lee, Wei -Hsiang Liao, Yu-Sheng Wang*, Chi-Cheng Hung*, Ying-Lang Wang*, National Cheng Kung University, *National Chiao Tung University
P-20 Improving Tungsten Gap-fill for Advanced Contact Metallization, K. Wu, S.H.Lee, V. Banthia, R. Hung, Applied Materials Corporation
P-21 Low-via-resistance and low-cost PVD-TiZrN barrier for Cu/low-K interconnects, Y.C. Chan, C.H. Peng, M.H. Lee, S.Y. Yang, C.F. Yeh, S.L. Shue, Taiwan Semiconductor Manufacturing Co, Ltd.
P-22 Vapor Deposition of Copper-Manganese Interconnects, R. G. Gordon, J. Feng, X. Gong, K. Li, Harvard University
P-23 Characterization of Advanced Sequential Flow Deposition (ASFD) TiON electrode in MIM structure for leakage current reduction, Tadahiro Ishizaka, Masaki Koizumi, Masaki Sano, Seokhyoung Hong, Masato Koizumi, Cheonsoo Han, Koji Akiyama*, Sara Aoki*, Kentaro Shiraga*, Tatsuhiko Tanimura*, Tokyo Electron Yamanashi Ltd.,*Tokyo Electron Ltd.
P-24 A novel bottom up fill mechanism for the metallization of advanced node copper interconnects, V.Mévellec, M. Thiam, D.Suhr, L. Religieux, P. Blondeau, J.B. Chaumont and F. Raynal, aveni
P-25 Process metrology of cobalt damascene interconnects, E. Shalyt, M. Palvov, X. Yan, D. Lin, ECI Technology, Inc.
P-26 Barrier Layer Dependence of Self-Annealing Effect in Directly Electroplated Copper Films, X. Wang, G. Yang, L. A. Cao, X. P. Qu, Fudan University
P-27 Dual Precursor Atmospheric Plasma Deposition of Bilayer Organosilicate Protective Coatings on Plastics, Siming Dong, Zhenlin Zhao, Reinhold H. Dauskardt, Stanford University
P-28 Spray Deposition of Compositionally Graded Hybrid Layers for High-Performance Adhesion, Yichuan Ding, Reinhold H. Dauskardt, Stanford University
P-29 Synthesis of Doped Carbon Nanotubes by CVD Using NiB Catalysts, K. Tomita, N. Kawakami, A. Aozasa, K. Aida, K. Ueno, Shibaura Institute of Technology
P-30 Multi-layer graphene interconnect – A feasibility study, M. Politou, X. Wu, A. Contino, B. Soree, C. Huyghebaert, D. Lin, I. Radu, Z. Tokei, I. Asselberghs, imec
P-31 Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias, A.A. Vyas, C.Y. Yang, P. Wang*, C. Zhou**, Y. Chai**, Santa Clara University, *Applied Materials Inc., **Hong Kong Polytechnic University
P-32 AFD-based Model of EM Lifetime and Reservoir Effect, Zhong Guan, Malgorzata Marek-Sadowska, UC Santa Barbara
P-33 Investigation on Reliability Improvement for Next Generation Cu/ULK Interconnects, Xun Gu, Jiquan Liu, Hao Deng, Zheyuan Tong, Jennifer Jing, Beichao Zhang, SMIC
Thursday, May 26
SESSION 12: 3D Systems
8:15 – 10:30
12.1 INVITED – On the Electrical Performance of Rigid Silicon Interposer, Farhang Yazdani, BroadPak Corp.
12.2 INVITED – Interconnect Roles for Emerging Memory Technologies in 3D Architecture, Er-Xuan Ping, Applied Materials
12.3 Nondestructive inspection and inline estimation of profiles of copper-filled through-silicon vias with voids by a nano-focus X-ray microscope, Yasutoshi Umehara and Nobuyuki Moronuki*, Tokyo Electron Ltd., *Tokyo Metropolitan University
12.4 Effect of Scaling Copper Through-Silicon Vias on Stress and Reliability for 3D Interconnects, Laura Spinella, Miseok Park, Nobumichi Tamura*, Tengfei Jiang**, Jang-hi Im and Paul Ho, University of Texas at Austin, *Lawrence Berkeley National Laboratory, **University of Central Florida
12.5 Numerical and Experimental Exploration of Thermal Isolation in 3D Systems Using Air Gap and Mechanically Flexible Interconnects, Yang Zhang, Thomas Sarvey, Yue Zhang, Muneeb Zia and Muhannad Bakir, Georgia Institute of Technology
SESSION 13: MUP-ILD II
10:45 – 12:30
13.1 Invited – Novel approaches to determine thermomechanical materials data in advanced interconnect stacks, Ehrenfried Zschech, Martin Gall, Andre Clausner, Christoph Sander, Valeriy Sukharev*, Fraunhofer Institute, *Mentor Graphics, Inc.
13.2 Pre-Liner Dielectric Nitridation for Resistance Reduction in Copper Interconnects, C.-C. Yang, T. Spooner, W. Wang, J. Maniscalco, P. McLaughlin, C.K. Hu, E. Liniger, T. Standaert, D. Canaperi, R. Quon, E. Huang and D. Edelstein, IBM Research
13.3 Ultrathin Conformal Multilayer SiNO Dielectric Cap for Capacitance Reduction in Cu/low k Interconnects, D. Priyadarshini, S. Nguyen, H. Shobha, S. Cohen*, T. Shaw*, C. Parks**, E. Adams**, J. Burnham**, E. Liniger*, C.K. Hu*, D. Collins***, T. Spooner, A. Grill*, D. Canaperi, V. Paruchuri, D. Edelstein*, IBM Research, Albany Nanotech, *IBM T.J. Watson Research Center, **GLOBALFOUNDRIES, ***Applied Materials Inc.
13.4 Thermomechanical Asymmetries in ULK Dielectric Glasses, Joseph Burg and Reinhold Dauskardt, Stanford University
SESSION 14: Reliability II
1:40 – 2:35
14.1 INVITED – Design-for-Stress for CMOS Technologies – The next frontier, Riko Radojcic, Consultant
14.2 Electrical properties and TDDB performance of Cu interconnects using ALD Ta(Al)N barrier and Ru liner for 7nm node and beyond, Yuki Kikuchi, Hiroaki Kawasaki, Hiroyuki Nagai, Kai-Hung Yu*, Manabu Oie*, Steven Consiglio*, Cory Wajda*, Kaoru Maekawa*, Gert Leusink*, Tokyo Electron Ltd., *TEL Technology Center, America, LLC.
SESSION 15: MUP-Metal II
2:50 – 4:35
15.1 INVITED – Materials Science of Ru and Ru Alloy Thin Films for Barrier Applications, Wen Liao, Daniel Bost, Chia-Yun Chiu, Gyeong Hwang and John Ekerdt, University of Texas at Austin
15.2 Tungsten and Cobalt Metallization: A Material Study for MOL Local Interconnects, V. Kamineni, M. Raymond, S. Siddiqui, F. Mont, S. Tsai, C. Niu, A. Labonte, C. Labelle, S. Fan*, B. Peethala*, P. Adusumilli*, R. Patlolla*, D. Priyadarshini*, Y. Mignot*, A. Carr*, S. Pancharatnam*, J. Shearer*, C. Surisetty*, J. Arnold*, D. Canaperi*, B. Haran*, H. Jagannathan*, F. Chafik**, B. L’Herron, GLOBALFOUNDRIES Inc., *IBM, **STMicroelectronics
15.3 Fluorine-Free Tungsten Films as Low Resistance Liners for Tungsten Fill Applications, Jonathan Bakke, Yu Lei, Yi Xu, Kazuya Daito, Xinyu Fu, Guoqiang Jian, Kai Wu, Raymond Hung, Rajkumar Jakkaraju and Nicolas Breil, Applied Materials
15.4 Development of electroless Co via-prefill to enable advanced BEOL metallization and via resistance reduction, Yu Jiang, Praveen Nalla, Yana Matsushita, Greg Harm, Jingyan Wang, Artur Kolics, Larry Zhao, Tom Mountsier, Paul Besser and Hui-Jung Wu, Lam Research Corporation
15.5 Is electron transport in nanocrystalline Cu interconnects surface dominated or grain boundary dominated? A first principles Density Functional Theory computational investigation, Ganesh Hegde, R. Chris Bowen and Mark S. Rodder, Samsung Semiconductor Inc.