8:30 – 9:40 a.m. Plenary Session
10:00 – 12:00 p.m. Novel Systems I
12:00 – 1:00 p.m. Conference Luncheon
1:00 – 2:30 p.m. Poster Session I
2:30 – 5:15 p.m. Materials and Unit Process I

8:30 – 10: 20 a.m. 3D Integration I
10:45 – 12:30 p.m. Reliability I
12:30 – 1:15 p.m. Conference Luncheon
1:15 – 2:45 p.m. Poster Session II
2:45 – 5:25 p.m. Process Integration

8:30 – 10:15 a.m. Materials and Unit Processes II
10:40 – 12:30 p.m. Novel Systems II
12:30 – 1:30 p.m. Conference Luncheon
1:30 – 2:45 p.m. Reliability II
3:10 – 5:20 p.m. 3D Integration II
5:20 – 5:30 p.m. Closing Remarks/Adjourn


8:30am – 9:40am
Wednesday, May 21

8:30am Welcome and Introduction

8:40am Keynote Presentation
Randhir Thakur
Executive Vice President and General Manager of the Silicon Systems Group
Applied Materials, Inc.


10:00AM – 12:00PM
Wednesday, May 21

2.1 – INVITED – Nanophotonic and Interconnects – Status and Future Directions, David A.B. Miller, Ginzton Laboratory, Stanford University, Stanford, CA

Optical interconnects at progressively shorter distances and higher communications densities demand novel optics and very low operating energies. Optoelectronics with femtojoule or lower energies and compact custom and self-designing optics may enable the lower energy per operation and higher bandwidth density required for continued scaling of information processing, with significant potential impact for systems. Novel approaches will be summarized.

2.2 – Interconnect Performance and Scaling Strategy at 7 nm Node, J. Chen, T. Standaert, E. Alptekin, T. Spooner, V. Paruchuri, IBM

In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit performance can be determined. The interconnect delay is plotted as a function of wire resistance, via resistance and capacitance. In order to better optimize the BEOL architecture, contour plots of resistance versus capacitance are presented in this paper. The result of this paper is indicating a strong dependency of circuit performance on the wiring length which is a new challenge. Optimization of BEOL architecture therefore requires a new approach which is outlined in this paper. As a result, we would like to bring this to the design community’s attention.

2.3 – INVITED – Overview of Embedded Packaging Technologies, Rajendra D. Pendse, STATSChipPAC Inc., Fremont, CA

Moore’s law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore’s law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.

2.4 – ESD Characterization and Design Guidelines for Interconnects in 28nm CMOS, Zongyu Dong, Fei Lu, Li Wang, Rui Ma, Chen Zhang, Hui Zhao, Albert Wang, Shijie Wen*, Rick Wong*, Rita Fung*, Charles Chu**, Jeff Watt**, Agha Jahanzeb***, Peter Liaw****, Dept. of EE, University of California, Riverside;*CISCO, San Jose, CA; **Altera, San Jose, CA; ***TI, Dallas, TX; ****Broadcom, San Jose, CA

This paper reports comprehensive transient electrostatic discharge (ESD) characterization of backend interconnects in a foundry 28nm CMOS. Testing results reveal details on metal current handling capability and on-chip ESD protection ability. ESD design guidelines for interconnects are provided for chip-level ESD protection circuit designs in 28nm CMOS.


Wednesday, May 21

3.1 – Through-Silicon-Via Material Property Variation Impact on Full-Chip Reliability and Timing,
Moongon Jung, David Z. Pan*, Sung Kyu Lim, Georgia Institute of Technology, *University of Texas at Austin

We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young’s modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.

3.2 – Growth Kinetics of Individual Al-Cu Intermetallic Compounds, Heinrich Koerner, Sergey Ananiev, Robert Bauer, Rui Huang, Roland Resel*, Yik Yee Tan**, Juergen Walter***, Infineon Technologies AG, Neubiberg, Germany, * Institute of Solid State Physics, Graz University of Technology, Austria, **Infineon Technologies, Melakka, Malaysia, *** Infineon Technologies AG, Regensburg, Germany

The growth kinetics of Al-Cu intermetallic compounds (IMC) have been investigated on thin film couples and bonded samples in the range 150°C to 250°C using XRD, SEM/EDX and in-situ interface resistance monitoring. Individual diffusion constants Do and activation energies Ea (1.01eV, 0.97eV, 1.23eV, 1.28eV) have been obtained from thin film couples for the main three IMC phases Al4Cu9, AlCu and Al2Cu, and for the total IMC growth, respectively. Two additional phases (Al3Cu2, Al0.06Cu0.94) contribute to the total IMC growth at T ≥ 200°C, but do not form at lower temperatures. Lower activation energies of 1.13eV (thin film) and 1.05eV (bonded samples) have thus been derived for T < 200°C for the overall IMC growth and are recom-mended to be used for lifetime predictions in the typical regime of device application temperatures.

3.3 – A Tri-axis MEMS Capacitive Sensor Using Multi-Layered High-density Metal for an Integrated CMOS-MEMS Accelerometer, D. Yamane, T. Konishi*, T. Matsushima*, H. Toshiyoshi**, K. Machida*, and K. Masu,Tokyo Institute of Technology, *NTT Advanced Technology Corp., **The University of Tokyo

This paper reports a novel tri-axis microelectromechanical systems (MEMS) capacitive sensor utilizing multi-layer electroplated gold. The high density of gold has enabled us to minimize the Brownian noise and hence to reduce the footprint of the proof mass. To optimize the flexibility of the mechanical springs for tri-axis motions, we have newly developed multi-layered metal spring structures. All the MEMS structures have been made by gold electroplating, used as a post complementary metal-oxide semiconductor (CMOS) process, and thereby the MEMS sensors can be implemented as integrated CMOS-MEMS accelerometers.

3.4 – Integration of ALD Barrier and CVD Ru Liner for Void Free PVD Cu Reflow Process on Sub-10nm node Technologies, K. Yu, T. Hasegawa M. Oie, F. Amano, S. Consiglio,C. Wajda, K. Maekawa and G. Leusink, TEL Technology Center, America, LLC

Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes. ALD barrier films were developed and integrated with a 2nm CVD-Ru (replacing the traditional PVD Ta and PVD Cu seed), and a single-step PVD Cu dry-fill process for bottom-up via and trench fill. Line resistance and barrier integrity data complement the Cu-fill performance.

3.5 – Study of void formation in Cu interconnects using local sense and standard single-via structure, G.Marti,L.Arnaud,Y.Wouters*,STmicroelectronics,*SIMAP-GRENOBLE

In this paper the void formation during electromigration is characterized with the innovative Local Sense Structure (LSS) and with a standard single-via (SSV) electromigration test. LSS allows to measure small resistance change before final void formation, that have allowed to define a time of nucleation of the void (Tn). Furthermore, the classic structure has been used to evaluate the time to failure and to study in detail the “plateau” of void formation, where we suppose the void nucleate. The comprehension of nucleation and others phenomena before the classic jump of resistance will be fundamental for the future of interconnects reliability physics and lifetime prediction.

3.6 – Synthesis and PEALD evaluation of New Nickel precursors, S.Gatineau, C.Ko, J.Gatineau, C.Lansalot*, C.F. Hsiao**, Air Liquide Laboratories, *Air Liquide Laboratories Korea, **Air Liquide Far Eastern

A new family of oxygen and fluorine free Nickel (Ni) precursors, which are based on allyl and alkylpyrrolyl-imine ligands [Ni(allyl)(PCAI-R)], has been developed and evaluated for a Ni metal film with thermal and plasma enhanced ALD using H2/NH3 as a reducing agent. From Ni(allyl)(PCAI-iPr), pure Ni film with very low resistivity (5.3 µΩ•cm) was obtained at 400 oC by PEALD, which is close to the resistivity value of bulk Nickel (5-10 μΩ•cm). The thermal properties of Ni precursors, the deposition results of thermal ALD and PEALD will be discussed

3.7 – A Self-Aligned Via Etch Process to Increase Yield and Reliability of 90 nm Pitch Critical Interconnects with Ultra-thin TiN Hardmask, J H Liao, Yu Tsung Lai, Brandon Kuo1*, Prabhakara Gopaladasu**, Scott Wang, Sean Yao, Kiki Wang, Ivan Wang, Paul Lin, Barrett Finch, Shashank Deshmukh, *Advanced Etch Department, United Microelectronics Corp., Tainan, Taiwan. R.O.C. **Lam Research Corporation, Fremont, USA

Back-end-of line (BEOL) interconnect scaling has led to the implementation of self-aligned via (SAV) schemes for ≤ 90 nm BEOL pitches. In one implementation of this scheme, a TiN metal hardmask (MHM) is used for the trench pattern definition while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines. In this work, we describe a SAV etch process that enables the use of thin (≤ 15 nm) TiN MHM. Key attributes of the via and trench etching process in a capacitively coupled etch reactor are described to meet physical performance requirements and eliminate tradeoffs between via chain yield and via-to-metal (M2-V1) bridging. Low-k sidewall damage, post-etch wet clean, and metallization are discussed. Finally, the physical etch performance is correlated to the device breakdown voltage (VBD) and time-dependent dielectric breakdown (TDDB) lifetime performance.

3.8 – The Effect of Crystal Phase of Ta Barrier on Via Resistance and Reliability Performance for Cu Line, K.Ohmori, S.Muranaka, K.Maekawa,M.Fujisawa, Renesas Electronics Corporation

In this study, we have investigated the influences of crystal phase of Ta barrier at the via bottom on via resistance and reliability performances. We found that the via resistance with 5nm-thick TaN under layer show bi-modal distribution. And we estimated that the bi-modal distribution of via resistance indicates the Ta crystal phase at via bottom become one of a-Ta and b-Ta. Also, we represented that the reliability performance is same for both α-Ta and β-Ta. These results indicate the influence of the phase of Ta in only the distribution of via-resistance.

3.9 – Plasma-Enhanced CVD Low-k Process Enabling Global Planarity by Controlling Flowability, Dai Ishikawa, Akinori Nakano, Shintaro Ueda, Hiroshi Kou, Hirofumi Arai, Akiko Kobayashi,Kiyohiro Matsushita, Nobuyoshi Kobayashi, ASM

Plasma-enhanced CVD (PECVD) flowable low-k process compatible with the conventional UV cure process has been developed. Reduction of shrinkage by the UV cure was critical to ensure gap-filling capability with planarity, which was achieved by deposition condition tuning to reduce hydro-carbon constituent in the film and enhancement of dehydration by applying post-deposition treatment. Complete filling of 45-nm-space trench was achieved with excellent global planarity.

3.10 – Wire Bond Pull Test and Its Correct Uses, Lan Li, Kevin Li, International Rectifier, Co.

This paper will be focus on the equilibrium principal of force and mathematical proof to establish a quantitative mathematical mode of bond pull strength in two wires. Further the correct hook position is quantitatively derived. This paper also defines a new parameter—Normalized Hook Position (NHP) which provides a more convenient and practiced method to locate the correct hook position. Finally as an engineering application of the mode, the adhesive strengths (peel resistances) exerted on the wire bonds were calculated quantitatively and simultaneously during destructive bond pull test.

3.11 – Direct Cu Plating of High Aspect Ratio Through Silicon Vias (TSVs) with Ru Seed on 300 mm Wafer, F. Wafula, G. Pattanaik, J. Enloe, K. Hummler*, B. Sapp*, Atotech USA Inc., *SEMATECH

In this paper, physical and electrical results of full wafer direct Cu plating of 2×40 µm TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech’s TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed.

3.12 – Flip-chip interconnects based on solution deposited carbon nanotube bumps, Pingye Xu, Michael C. Hamilton, Auburn University.

A solution based fabrication process of carbon nanotube (CNT) bump interconnects is proposed. In comparison to CVD growth of CNT which requires high process temperature, the proposed process has the advantage of being capable to fabricate CNT bumps at room temperature with relatively high resolution and adjustable bump height. The average resistance of the fabricated CNT bumps was measured to be 904 mΩ, comparable to the resistance of the transferred CVD grown CNT bumps.

3.13 – Reliability Analysis of Bumping Schemes under Chip Package Interaction, Sri Ramakanth Kappaganthu, Aditya Karmarkar, Xiaopeng Xu*, Karim El Sayed*, Ibrahim Avci*, Vikas Chawla*, Bikash Mishra*, Andrey Kucherov*, Weixing Zhou*, Mark Johnson*, Pratheep Balasingam*, Synopsys (India) Private Limited, *Synopsys, Inc.

Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties.

3.14 – HF etching mechanisms of advanced low-k films, P. Verdonck, Quoc Toan Le, M. Krishtab, K. Vanstreels, S. Armini, A. Simone, Mai Phuong Nguyen, M. R. Baklanov, S. Van Elshocht, imec

Scaling of the Cu interconnect structures requires low-k materials which also have an adequate Young’s modulus (e.g. E > 6 GPa) and good chemical resistance. This last characteristic can be determined through HF wet etching tests. In this paper, different types of low-k films (k-value range: 2.0-2.3; E range: 2 – 9 GPa) were immersed in a 0.5 volume % HF solution. The HF etching behaviour proved to be very dependent on the wetting properties of the film: even with lower Si-CH3 content, the film with highest water contact angle (i.e. most hydrophobic surface) was the most resistant against the HF etching.

3.15 –Localization length of integrated multi-walled carbon nanotubes, Holger Fiedler, Sascha Hermann, Michael Rennau; Technische Universität Chemnitz, Center for Microtechnologies (ZFM), Stefan E. Schulz, Thomas Gessner , Technische Universität Chemnitz, Center for Microtechnologies (ZFM), and Fraunhofer Institute for Electronic Nano Systems, Chemnitz, Germany

We prepared CNT based vias on wafer scale. Based on the electrical characterization we extracted the localization length of the CNTs. While for short CNTs the classical transport regime is valid, the Anderson localization regime applies for longer CNTs. Supplementary the characteristic length scales were estimated based on the structure of the CNTs being in good agreement with the parameters extracted from the electrical measurements.

3.16 – Design of Multilevel Interconnect Network of an ASIC Macrocell for 7.5nm Technology Node Using Carbon Based Interconnects, E. Kishani Farahani, R. Sarvari, Sharif University of Technology

Multilevel interconnect network of a macrocell for 7.5 nm technology node is designed with carbon based interconnects (CBI) and Cu. Results are compared. Constrains of using CBI is discussed. It is shown that by using CBI power dissipation associated with wires could decrease by 32%. To use GNRs for more than one metal pair, reverse wire pitch idea is proposed that prevents undesirable increase in the number of metal layers.

3.17 – Cu barrier properties of very thin Ta and TaN films, H. Wojcik, B. Schwiegel*, C. Klaus, N. Urbansky*, J. Kriz*, J. Hahn*, C. Kubasch, C. Wenzel, J. W. Bartha, Institutefor Semiconductor & Microsystems Technology, Technische Universität Dresden, Dresden, Germany; *Infineon Technologies GmbH, Dresden,Germany

This paper reports on the Cu barrier performance of very thin Ta and TaN films (1 to 3nm) deposited by PVD DC magnetron sputtering on different types of dielectrics. The barrier evaluation itself consisted of a combination of an initial thermal anneal, electrical bias temperature stress (BTS) and triangular voltage sweep (TVS) measurements. It was found that a 1nm Ta layer deposited on PECVD silane SiO2 withstands Cu diffusion during 1h 600 °C anneal and BTS at 300 °C, +2 MV/cm for 1800 s, whereas even a 3nm Ta layer deposited on thermal SiO2 could not prevent Cu diffusion or field drift, already after 1h 350 °C annealing. As a hypothesis, it is assumed that oxygen is stuffing grain boundaries or defects.


Wednesday, May 21

4.1 –INVITED – Alternative Metals for Advanced Interconnects, Christoph Adelmann, Liang Gong Wen, Antony Premkumar Peter, Yong Kong Siew, Kristof Croes, Johan Swerts, Mihaela Popovici, Kiroubanand Sankaran, Geoffrey Pourtois, Sven Van Elshocht, Jürgen Bömmels, Zsolt Tőkei, Imec, Leuven, Belgium

We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides, such as CoGe2, Cu3Ge, or NiGe, as well as CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.

4.2 – Demonstration of a Sidewall Capacitor to Evaluate Dielectrics and Metal Barrier Thin Films, Kevin L. Lin, Colin T. Carver, Ramanan Chebiam, James Clarke, Jacob Faber, Michael Harmes, Tejaswi Indukuri, Christopher Jezewski, Mauro Kobrinsky, Brian Krist, Narendra Lakamraju, Hazel Lang, Alan M. Myers, John J. Plombon, Kanwal Jit Singh, Hui Jae Yoo, Intel Corporation

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

4.3 – Electron Mean-Free Path for CNT in Vertical Interconnects Approaches Cu, M.H. van der Veen, Y. Barbarin, Y. Kashiwagi**, Zs. Tökei, imec, ** Tokyo Electron Ltd.

A CNT contact length scaling is used to derive the electron mean-free path (λCNT) after full integration. A CNT-to-metal contact resistance of 76 Ω and lower was obtained for 150 nm diameter contacts. By estimating the number of conducting walls in the CNT bundle, a λCNT of 74 nm is found, which is longer than for Cu. We propose a more conservative approach of calculating λCNT solely from electrical data. The result is that our CNT interconnects have ballistic transport over 24 nm, which is 5 times longer than reported so far.

4.4 – Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects, Deepika Priyadarshini*, S. Nguyen*, H. Shobha*, S. Cohen**, T. Shaw**, E. Liniger**, C.K. Hu**, C. Parks***, E. Adams#, J. Burnham#, A.H. Simon***, G. Bonilla**, A. Grill**, D. Canaperi*, D. Edelstein**, D. Collins##, M. Balseanu##, M. Stolfi##, J. Ren##, K. Shah##, *IBM Research, Albany, NY, **IBM T.J. Watson Research Center, Yorktown Heights, NY, ***IBM STG Hopewell Junction, NY, #IBM STG, Essex Junction, VT, ##Applied Materials Inc., Albany, NY, and Santa Clara, CA

Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ pre-clean/metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

4.5 – Sub-10-nm-wide intercalated multi-layer graphene interconnects with low resistivity, D. Kondo, H. Nakano, B. Zhou, A. I, K. Hayashi, M. Takahashi, S. Sato, N. Yokoyama, AIST

We fabricated sub-10-nm-wide intercalated multi-layer graphene (MLG) interconnects and demonstrated a resistivity lower than that of Cu interconnects with similar dimensions. The high-quality MLG synthesized by chemical vapor deposition was intercalated with FeCl3. After narrowing down, the 8-nm-wide intercalated MLG exhibited a resistivity of 3.2 μΩcm, which is predicted to be lower than that of Cu interconnects with the same dimensions. Our results show that intercalated MLG is really promising for future LSI interconnects.

4.6 – Exploring Alternative Metals to Cu and W for Interconnects: an ab initio Insight, K. Sankaran, S. Clima, M. Mees*, C. Adelmann, Z. Tokei, G. Pourtois**, imec, * KU Leuven, **University of Antwerp

This paper deals with the computation of the properties of alternative metals to Cu and W for interconnect applications. These are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.


Thursday, May 22

5.1 – INVITED – Challenges to Via Middle TSV Integration at Sub-28nm Nodes, H.Kamineni, S.Kannan, R.Alapati, S.Thangaraju, D.Smith, D.Zhang, S.Gao, GLOBALFOUNDRIES, Inc.

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

5.2 – Novel Stress-Free Keep Out Zone Process Development for Via Middle TSV in 20nm Planar CMOS Technology, Mohamed A. Rabie, Premachandran C. S., Rakesh Ranjan, Mahadevan Iyer Natarajan, Sing Fui Yap, Daniel Smith, Sarasvathi Thangaraju, Ramakanth Alapati, Francis Benistant, GLOBALFOUNDRIES Inc., USA

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3ppm/◦C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.

5.3 – Electroless Cu Seed on Ru and Co Liners in High Aspect Ratio TSV, F. Inoue, H. Philipsen, M. H. van der Veen, S. Van Huylenbroeck, S. Armini, H. Struyf, T. Tanaka*, IMEC, *Tohoku University

High aspect ratio through-silicon vias (3 mdiameter by 50 m depth) have been filled by conformal Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.

5.4 – INVITED – 3D Integration Technology using Hybrid Wafer Bonding and Via-last TSV Process, Kenichi Takeda and Mayu Aoki, Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan

A three-layer-stacked wafer with CMOS devices was fabricated by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings seamless copper bonding in face-to-face (F2F) and back-to-face (B2F) configurations. The low capacitance of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV.


10:45AM – 12:30PM
Thursday, May 22

6.1 – INVITED – Reliability of Ultra-Porous Low-k Materials for Advanced Interconnects,
J. L. Plawsky, J. Borja, T-M. Lu, W.N. Gill, RPI, H. Bakhru, R.Rosenberg, SUNY-CNSE, T. M. Shaw, E.G. Liniger, S.A. Cohen, G. Bonilla, IBM, R. B. Laibowitz, Columbia U

The paper discusses the results of dynamic field tests designed to separate electronic versus ionic conduction mechanisms, understand the degree and time dependence of charge trapping in dielectrics, and relate those measurements to dielectric breakdown and interconnect reliability.

6.2 – Analysis of time-dependent clustering model to BEOL TDDB, R. Achanta, E.Wu, B.Li, P.McLaughlin, IBM Microelectronics Division

Recently, a time-dependent clustering model has been reported showing good agreement with multiple sets of experimental TDDB data by proper consideration of the percentile scaling of different areas (vertical translation in the Weibull scale) [1,2]. In this work, we investigate the scaling property (horizontal translation) of time-to-fail (TFAIL) for different areas. Our results indicate that both the horizontal and vertical scaling properties for area transformation are preserved in the clustering model, showing its potential to replace the Weibull model. Moreover, we demonstrate the applicability of the time-dependent clustering model to bi-modal TDDB data, often encountered in practice. Finally, we develop a successive breakdown theory in the framework of the clustering model and compare it with experimental BEOL TDDB data.

6.3 – Performance of Ultrathin Alternative Diffusion Barrier Metals for Next -Generation BEOL Technologies, and their Effects on Reliability, T. Nogami, M. Chae*, C. Penny, T. Shaw, H. Shobha, J. Li, S. Cohen, C-K. Hu, X. Zhang*, M. He*, K. Tanwar*, R. Patlolla, S-T. Chen, J. Kelly, X. Lin*, O. Straten, A. Simon, K. Motoyama, G. Bonilla, E. Huang, T. Spooner, and D. Edelstein, IBM, *GLOBALFOUNDRIES Inc.

In order to maximize Cu volume and reduce via re-sistance, barrier thickness reduction is a strong option. Alternative barriers for next-generation BEOL were evaluated in terms of barrier performance to O2 and Cu diffusion, and effects on reliability. A clear correla-tion of O2 barrier performance to electromigration was observed, suggesting that the key role of the barrier layer is to prevent oxidation of Cu or the Cu/barrier interface. Long-throw PVD-TaN showed superior O2 barrier performance to alternative metals such as PEALD-TaN, thermal ALD-TaN, -TaN(Mn) and –MnN and MnSiO3 self-forming barrier.

6.4 – EM performance upside of short BEOL interconnects in advanced process technologies: Electrical-Thermal Finite Element Simulations and Silicon Verifications, Jinseok Kim, Tae-Young Jeong, Yunhee Jo, Kyuho Tak, Miji Lee, Sari Windu, Hyunjun Choi, Chungil Son, Yunkyung Jo, Minsung Kim, Jun-Kyun Park, Sangwoo Pae and Jongwoo Park,Samsung Electronics Corp.

In this paper, thermal characteristics (Joule heating) induced by currents in short metal interconnect lines are studied. Electrical-thermal 3D-Finite Element Method (FEM) simulation is employed to model the property of temperature in short length metal lines and an empirical yet practical current model with metal line length effect is introduced. Consequently, the Irms current gain up to 25% in short length metal was achieved. This is attributed to the heat dissipation at the line end being much more effective in short metal lines compared to long metal lines. The material properties of interconnects for simulation was obtained using 64nm pitch BEOL process. The simulation results were verified with experiment silicon data using metal test structures.


1:15PM – 2:45PM
Thursday, May 22

7.1 – Unique nondestructive inline metrology of TSVs by X-ray with model based library method, Y. Umehara, Tokyo Electron Inc. and W. Jin, Tokyo Electron America Inc.

Unique nondestructive inline profile metrology of TSVs for 3D integrated circuits in production processes such as ultra-deep etching and Cu pillar forming process was introduced. We tried to measure the depth profile of TSVs from X-ray images with a tilted angle by applying model based library method. The fairly good repeatability ( <0.1um, <0.2um respectively) and good correlation in CDs with results from SEM measurement were obtained, and good robustness under low SNR ~2 of the images was confirmed.

7.2 – Organosilicate Glass Dielectric Films with Backbone Carbon: Enhanced Resistance to Carbon Loss in Plasma Environments, H. Kazi, R. James, S. Gaddam, U. Chiluwal, J. Rimsza, J. Du and J. Kelber, Center for Electronic Materials Processing and Integration, University of North Texas

X-ray photoelectron spectroscopy data indicate that organosilicate glass (OSG) films with backbone carbon (Si-R-Si) exhibit significantly enhanced resistance to carbon loss upon exposure to either atomic oxygen or to vacuum ultraviolet light in the presence of O2 compared to films with terminal methyl groups (Si-CH3). These results and comparisons to ab initio molecular dynamics simulations indicate –Si-R-Si- films exhibit fundamentally different Si-C bond-breaking mechanisms, with more resistance to carbon loss, compared to Si-CH3 films.

7.3 – Highly Compressed Nano-Layers in Epitaxial Silicon Carbide Membranes for MEMs Sensors, R. Brock, F. Iacopi*, A. Iacopi*, L. Hold*, R.H. Dauskardt, Stanford University, *Griffith University

Through a novel methodology for evaluating layer-by-layer residual stresses in epitaxial silicon carbide films with resolution down to 10 nm, we indicate the existence of a highly compressed interfacial nano-layer between the films and their silicon substrates. This layer is consistently present underneath all types of silicon carbide films examined herein, regardless of the extent of residual tensile stress measured in the full thickness of the films, which varies from 300 MPa up to 1300 MPa. We link this nano-layer to the carbonisation step of the film growth process and we discuss in detail the implications in terms of fracture behaviour by bulge testing of micro-machined membranes.

7.4 – Atomic Flux Divergence Based Current Conversion Scheme for Signal Line Electromigration Reliability Assessment, Z. Guan, M. Marek-Sadowska1, S. Nassif*, B. Li**, University of California Santa Barbara, *IBM Research Lab, **IBM Systems and Technology Group

In this paper, we study electromigration (EM) reliability of signal lines. We propose a general model for current conversion from pulsed DC to steady DC based on the consistency of maximal atomic flux divergence. Both long and short lead lines with high frequency current are considered. The calculated effective steady DC agrees with the measured results. Our conversion scheme can be applied also to signal lines with complex current paths.

7.5 – Investigation Xe Pre-Amorphization Implantation on Nickel Silicide Formation, Pin Hong Chen, Chia Chang Hsu, Jerander Lai, Boris Liao, Chun Ling Lin, Olivia Huang, Chun Chieh Chiu, C. M. Hsu, J. Y. Wu, UMC

Xe pre-amorphization implantation (PAI) of various energy and dosage are used on Ni-Silicide formation, which has achieved amorphism-like NiSi films. The electric characteristic, physical morphology and metallurgical of the NiSi were identified by sheet resistance, grazing incident X-ray diffraction (GIXRD), and selected-area electron diffraction (SAD) analysis. Result shows that lower energy and higher dosage of Xe implantation can get amorphism-like NiSi film. The characteristic of small grain NiSi films can get smooth etching bottom profile benefiting process window of contact trench etching.

7.6 – Thermal stress control in Cu Interconnects, C.-C. Yang,B. Li, F. Baumann, P. Wang, J. Li, R. Rosenberg, and D. Edelstein, IBM

Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 ◦C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 ◦C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.

7.7 – Study of a single layer ultrathin CoMo film as a direct plateable adhesion/barrier layer for next generation interconnect, Xin-Ping Qu*, Xu Wang, Li-Ao Cao, Wen-Zhong Xu

In this work, a novel single layer CoMo alloy film is investigated as an excellent adhesion/diffusion barrier to copper metallization. The ultrathin (<3nm) CoMo film can withstand 400C/30min annealing on the ULK(k =2.25) and the electrical barrier properties on the p-cap SiO2 structure for the Cu/CoMo can be even better than the Cu/Ta/TaN structure. The CMP of the CoMo film are studied and the direct Cu electroplating on the CoMo film are demonstrated.

7.8 – Selective Formation of an Ultra-Thin Pore Seal on Mesoporous Low-k for a Copper Dual Damascene Structure, Y. Kayaba, H. Tanaka, T. Suzuki, K. Kohmura, S. Ono, Mitsui Chemicals, Inc.

A strategy for the selective formation of a pore sealing layer on mesoporous low-k applicable for Cu dual damascene interconnection process is proposed. An ultra-thin, adhesive, and conformal sealing layer was formed by spin coating macromolecules. The sealant on the Cu surface was selectively decomposed with the help of Cu2O induced oxidization. This selectivity was also examined for patterned structure. Our simple and novel technique will help the integration of ulta-low-k materials in LSI devices.

7.9 – Electromigration Induced Failure of Solder Bumps and the Role of IMC, H. Ceric, S. Selberherr, Institute for Microelectronics, Vienna University of Technology

Characteristic for solder bumps is that during technology processing and usage their material composition changes. We present a model for describing the growth of an intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.

7.10 – Permanent and Bumpless Wafer to Wafer Bonding Technologies Development for Low Cost 3DIC Wide I/O Memory Cube, Erh-Hao Chen, Jui-Chin Chen, Cha-Hsin Lin, Pei-Jer Tzeng, Chung-Chih Wang, Shang-Chun Chen, Tzu-Chien Hsu, Chien-Chou Chen, Yu-Chen Hsin, Po-Chih Chang, Yiu-Hsiang Chang, Sue-Chen Liao, and Tzu-Kun Ku, Industrial Technology Research Institute

A simple multiple permanent and bumpless wafer to wafer (PBWW) bonding through silicon via (TSV) integration processes with a 300mm wafer size are investigated to achieve a low cost three dimension integrated circuit (3DIC) stacked chips. This technology will be applied to the homogeneous dynamic random access memory (DRAM) wafers first. Key process modules such as chemical mechanical planarization (CMP) and TSV technologies are also developed and employed to reach the 3-layer bumpless wafer to wafer (W2W) stacking without complicated temporally bonding/debonding processes.

7.11 – The addition of aluminium and manganese to ruthenium liner layers for use as a copper diffusion barrier, A.P. McCoy, J. Bogan, C. Byrne, G. Hughes, P. Casey, J.G. Lozano*, P.D. Nellist*, Dublin City University, *University of Oxford

The chemical interaction of Al and Mn deposited on Ru thin films for use as copper diffusion barrier layers are assessed in-situ using x-ray photoelectron spectroscopy (XPS). Thin (~1-2 nm) Al and Mn films were separately deposited on 3 nm Ru liner layers on SiO2, and both Al/Ru/SiO2 and Mn/Ru/SiO2 structures were subsequently thermally annealed. Results indicate the diffusion of both metals through the Ru thin films and the subsequent chemical interaction with the underlying SiO2 substrate to form Al2O3 and MnSiO3.

7.12 – Cu Pattern Etching by Oxygen Gas Cluster Ion Beams with Acetic Acid Vapor, N. Toyoda, M. Kojima, R. Hinoura, A. Yamaguchi, I. Yamada*, K. Hara**, *University of Hyogo, **Tokyo electron Ltd.

Halogen free and low-temperature Cu etching was carried out using gas cluster ion beam (GCIB) with acetic acid vapor. A very shallow Cu surface was oxidized by O2-GCIB. Simultaneously, reactions between CuO and acetic acid occurred, and reaction products were desorbed by local heating of O2-GCIB irradiation. Thus, Cu etching at low-temperature (<60 °C) was achieved. From SEM images of Cu pattern with line width of 100 nm, anisotropic Cu etching was performed with this technique.

7.13 – Extreme filling in Alkaline Electrolytes, D. Josell, T.P. Moffat

Superconformal electrodeposition enables the fabrication of high aspect ratio interconnects that are ubiquitous in microelectronics. The Curvature Enhanced Accelerator Coverage (CEAC) mechanism captures the morphological and kinetic aspects of many “superfilling” processes for Damascene interconnect fabrication. Present superfilling copper electrolytes are acidic. Alkaline chemistries might rely on a non-CEAC filling mechanism.

7.14 – Selective Carbon Nanotube Growth in Via Structure Utilizing Novel Arrangement of Catalytic Metal, M. Wada, B. Ito, T. Saito, D. Nishide, T. Ishikura, A. Isobayashi, M. Katagiri, Y. Yamazaki, T. Matsumoto, M. Kitamura, L. Zhang, M. Watanabe, N. Sakuma, A. Kajita, and T. Sakai, Low-power Electronics Association & Project

The present work demonstrated the fabrication of CNT via structure on 300mm wafer. CNT-CMP behavior was investigated in an actual via pattern structure and we clarified technical issues of CNT-CMP process. We developed a new fabrication process of CNT via structure using selective CNT growth which has high potential for applying CNT to high A/R via structure.

7.15 – Impact of Pattern Density on Copper Interconnects Barrier Metal Liner Integrity, Wanbing YI, Daxiang WANG, Kemao LIN, Shaoqiang ZHANG, Juan Boon TAN, GLOBALFOUNDRIES Singapore

The dependency of Cu interconnects barrier metal liner integrity due to neighboring pattern density is presented in this paper. It was found that TaN/Ta bi-layer barrier metal liner on isolated Cu interconnects was oxidized. An elaborate study on the neighboring interconnects pattern density as well as process solutions were explored to investigate the impacts on the metal liner. Results showed that there is an obvious pattern density correlation with the integrity of the metal liner

7.16 – Ultra-Broadband Chip-to-Chip Interconnects to 220 GHz for Si-based Millimeter-Wave Systems, D. Kopp, M. Khan, G. Bernstein, and P. Fay, University of Notre Dame

Millimeter-wave chip-to-chip interconnects based on the Quilt Packaging approach are demonstrated for Si-based ICs. Chip-to-chip interconnects on high-resistivity silicon substrates have been measured to 220 GHz, and are compared with electromagnetic simulations. Single-mode, resonance-free operation is demonstrated through 220 GHz, with insertion loss below 1.5 dB over the full frequency range. Simulations indicate that with improvements to the joining method, insertion loss of less than 1 dB at 220 GHz is possible.


2:45PM – 5:25PM
Thursday, May 22

8.1 – INVITED – Integration of a 3-D Capacitor into a Logic Interconnect Stack for High performance Embedded DRAM SoC Technology, R. Brain, N. Bisnik, H.-P. Chen, J. Neulinger, N. Lindert, J. Peach, L. Rockford, Y. Wang, K. Zhang, Logic Technology Development, Intel Corporation, Hillsboro, OR

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >100μs retention at 95C. The process technology utilizes our leading edge 22nm 3-D tri-gate transistor as described previously [1-4]. We review the interconnect choices to enable the implementation of a high-aspect ratio 3-D capacitor into a SoC interconnect stack. Results will be reported for a test-vehicle with best-reported array density at 17.5Mb/mm2 based on a 128Mb macro in a 1Gbit eDRAM testchip [5].

8.2 – System-level Variation Analysis for Interconnection Networks, C. Pan, A. Naeemi, Georgia Institute of Technology

This paper analyzes the impact of interconnect variation at the system-level in terms of clock frequency based on a fast and efficient system-level design methodology. Various types of interconnect variations are compared, including the overlay, critical dimension (CD), and inter-layer dielectric variations. The results indicate that the CD variation has a larger impact on the overall clock frequency of the processor, especially for a logic core at a smaller technology node.

8.3 – INVITED – Contact module at dense gate pitch technology challenges, S. Demuynck, M. Mao, E. Kunnen, J. Versluijs, K. Croes, C. Wu, M. Schaekers, A. Peter, T. Kauerauf, L. Teugels, J. Bömmels, imec, Leuven, Belgium

In this paper we elaborate on challenges faced by contact formation at dense pitch: maintaining gate-to-contact reliability and keeping contact resistance low. We investigate intrinsic and integrated reliability of the gate-to-contact spacing materials and demonstrate capability of nitride gate encapsulation combined with a self-aligned contact etch process to handle misaligned contacts. Resistance of a silicide-through contact process is evaluated on fin substrates.

8.4 – Cu Wire Resistance Improvement using Mn-based Self-Formed Barriers, Y. K. SIEW, N. Jourdan, I. Ciofi, K. Croes, C. J. Wilson, B. J. Tang, S. Demuynck, #Z. Wu, #H. Ai, *D. Cellier, *A. Cockburn, J. Bömmels and Zs. Tőkei, Imec vzw, *Applied Materials Belgium, #Applied Materials

Cu wire resistance reduction using CVD Mn-based Self-Formed Barrier (SFB) compared to conventional PVD barrier was investigated at 40 and 100nm half pitch (HP). Mn-based SFB leads to both (1) maximum fractional Cu area in the trenches and (2) Cu resistivity reduction at scaled dimensions. This represents a breakthrough for future interconnect scaling. Blanket Cu experiments suggest that the Cu resistivity reduction in the case of Mn-based SFB can be attributed to lower surface scattering at the dielectric/Cu interface. Finally, promising reliability has been demonstrated in 20nm HP single damascene (SD) SiO2 trenches integrated with Mn-based SFB.

8.5 – Atomic Layer Deposition of MnOx for Cu capping layer in Cu/low-k interconnects, H. Kawasaki, K. Matsumoto, H. Nagai, Y. Kikuchi, P. Chang, Tokyo Electron Ltd.

We demonstrated atomic layer deposition (ALD) of manganese oxide (MnOx) for Cu capping layer. This process is expected to have not only EM (electro-migration) improvement but also admissibility of surface Cu oxidation. That will provide easy time and atmosphere management after chemical mechanical polishing (CMP). In this study, we confirmed Mn(Ox) coverage on Cu without degradation of leakage current and indication of EM improvement with simple EM test.

8.6 – INVITED – Advancements with Carbon Nanotube Digital Systems, M. Shulaker, G. Hills, H. Wei, H-Y. Chen, N. Patil, H-S.P. Wong, S. Mitra, Stanford University, Stanford, CA

Carbon Nanotube FETs (CNFETs) are excellent candidates for the next generation of high-performance and energy-efficient electronics, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. This paper presents an overview of the first demonstration of a computer implemented entirely using CNFETs. The CNT computer is capable of performing multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we emulate 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This is the most complex carbon-based electronic system yet demonstrated. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems. In addition to performance and energy benefits, CNFETs also provide a unique opportunity to achieve monolithic three-dimensional (3D) integration through low-temperature CNFET processing. Monolithic 3D integration is an attractive technological option because it enables a very high density of Inter-Layer Vias compared to Through-Silicon Vias. A summary of monolithic 3D CNFET integrated circuit demonstrations will also be given.


8:30AM – 10:15AM
Friday, May 23

9.1 – INVITED -Atomic Layer Deposition of Ultrathin and Continuous Metal Films, Steve George, University of Colorado

The atomic layer deposition (ALD) of ultrathin and continuous metal films is very challenging. This paper describes a general procedure that can yield an ultrathin and continuous metal ALD film using a W ALD adhesion layer.

9.2 – Resistance reduction of CNTs on 300-mm wafer by using two precursors with different growth methods, T. Saito, M. Wada, A. Isobayashi, D. Nishide, B. Ito, Y. Yamazaki, T. Matsumoto, N. Sakuma, A. Kajita, T. Sakai, Low-power Electronics Association & Project (LEAP)

The process conditions for improving the electrical properties of carbon nanotubes (CNTs) were investigated by using a blanket-structure method for quantifying CNT resistance independently. The growth mechanism of CNTs formed with two different gas precursors was investigated from the viewpoint of crystallinity, growth-length uniformity, and resistance. It was found that the resistance of CNTs is reduced by using a two-step growth method that produces a multi-wall CNT structure and a uniform micrometer-order growth length.

9.3 – Photoemission study of the impact of carbon content on Mn silicate barrier formation on low-k dielectric materials., J.Bogan, A.P.McCoy, P.Casey, R.O’Connor, C.Byrne, G.Hughes, Dublin City University

Ultra-thin Si and MnO films were deposited on a range of low dielectrics in order to accurately determine the binding energy positions of the Si2p and O1s photoemission peaks as a function of carbon concentration. Results show a measurable correlation between carbon content and BE position of both the Si2p and O1s core level peaks. In a separate set of experiments, the formation of a MnSiO3 on these substrates is inferred from analysis of the O1s and Mn2p spectra.

9.4 – Restoration and Pore Sealing of Low-k Films by UV-Assisted Processes, Bo Xie, Kelvin Chan, David Cui, He Ren, Daemian Raj, Eric Hollar, Sanjeev Baluja, Juan Rocha, Mehul Naik, and Alex Demos, Applied Materials, Inc., Santa Clara, CA

Porous low-k dielectrics are susceptible to damages by steps such as etch, ash, and CMP in the BEOL process flow. Such damages degrade the structural and electrical properties of low-k materials. To uphold the value of integrating low-k dielectrics, restoration processes are needed to repair such damages. In this work, UV-assisted silylation is used to repair damages and restore properties of porous low-k dielectrics. The repair process is able to restore carbon content, as indicated by the increase in water contact angle (WCA), and restore the electrical properties, as shown by the decrease in dielectric constant (k) and increase in break-down electrical field based on blanket-film data. On structured wafers, the post-etch repair process effects a 4-6% reduction in RC when compared to without repair. The same UV-assisted platform may be used to effect pore sealing to prevent metals used in BEOL metallization from penetrating into porous low-k materials. On structured wafers, the pore-sealing process is able to reduce Mn penetration into porous low-k when ALD MnN is used as the copper barrier


10:40AM – 12:30PM
Friday, May 23

10.1 – INVITED – Interconnects Scaling Challenge for Sub-20nm Spin Torque Transfer Magnetic Random Access Memory Technology, T. Min, Zs. Tokei, G.S. Kar, S. Coseman, J. Bekaert, P. Raghavan, S. Cornelissen, K.Xu, L. Souriau, D. Radisic, J. Swerts, T. Tahmasebi, and S. Mertens, imec, Leuven, Belgium

The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.

10.2 – Impact of Size Effects in Local Interconnects for Future Technology Nodes: A Study Based on Full-Chip Layouts, A. Ceyhan, M. Jung, S. Panth, S.K. Lim, A. Naeemi, Georgia Institute of Technology

In this paper, we investigate the impact of local interconnect size effects on the power dissipation of integrated circuits (ICs) based on timing-closed GDSII-level layouts of circuit blocks with detailed routing. For this purpose, we create multiple standard cell and interconnect libraries for 45-, 22-, 11- and 7-nm technology nodes considering scaling trends projected by the International Technology Roadmap for Semiconductors (ITRS) and assuming various sets of size effect parameters. We make iso-performance comparisons between circuit designs that are implemented using these libraries.

10.3 – INVITED – Switching and Reliability Mechanisms for ReRAM, Zhiqiang Wei*, Takeki Ninomiya**, Shunsaku Muraoka**, Koji Katayama*,Ryutaro Yasuhara*, and Takumi Mikawa*, *R&D Division, Panasonic Corporation, **Corporate Engineering Division, Automotive& Industrial Systems Company, Panasonic Corporation

Taking advantage of electron hopping between oxygen vacancies in filaments, ReRAM switching is caused by oxygen vacancy migration. We have developed an oxygen diffusion retention model, based on this switching mechanism, for both typical bits and outlier bits. Degradation of resistance of typical bits is due to the oxygen vacancy profile in the filament changing during oxygen diffusion, and the retention failure of outlier bits is caused by the critical percolation path being broken within the filament during oxygen diffusion.

10.4 – Impact of Dimensional Scaling and Size Effects on Beyond CMOS All-Spin Logic Interconnects, Rouhollah Mousavi Iraei, Phillip Bonhomme, Nickvash Kani, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Azad Naeemi, Georgia Institute of Technology, Georgia Institute of Technology, Georgia Institute of Technology,Intel Corporation, Intel Corporation, Intel Corporation, Georgia Institute of Technology

The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.


1:30PM – 2:45PM
Friday, May 23

11.1 – Moisture-Assisted Failure Mechanisms in Underfill Epoxy/Silicon Systems for Microelectronic Packaging, M. Giachino, R.H. Dauskardt, F. Paredes, S.M. Liff*, N. Ananthakrishnan*, Stanford University, Intel Coporation*

Synergistic effects of moisture and mechanical stress on debond kinetics of underfill epoxies used in semiconductor packaging are increasingly understood, however, the dramatic effect of increasing both temperature and humidity is not well known. We characterize the cohesive and adhesive properties of underfill epoxies containing a wide range of filler particles to an adjacent passivated silicon substrate and report on the moisture-assisted debonding kinetics in varying humidity and temperature environments, including accelerated testing conditions.

11.2 – Electrical Parametric and Reliability of 5×50um TSVs for 3D IC, Bharat Bhushan, Chin Hock Toh, Anthony Chan, Isaac Ow, Loke Yuen Wong, Arkajit Roy Barman, Shalina Sudheeran, Chandra Rao, Wahab Mohammed Abdul, Jason Chew, Jay Vijayen, Uday Mahajan, David Ericson, Niranjan Kumar, Sesh Ramaswami, Arvind Sundarrajan, Applied Materials Inc.

We present electrical parametric and reliability of 5×50um through silicon vias (TSVs) for three dimensional integrated circuits (3D IC). Electrical parameters such as oxide breakdown voltage (V_bd^TSV), leakage current (I_leak^TSV), oxide capacitance (C_ox^TSV), dielectric constant (k), minimum capacitance (C_min^TSV), threshold voltage (V_th) and mobile oxide charges (Q_m) of blind TSVs are analyzed. And, the reliability of TSVs is analyzed with thermal cycling between -55ºC to 125ºC with a dwell time of 10-15 minutes by following JEDEC standard No. 22-A104D.

11.3 – Reliability of Segmented Edge Seal Ring for RF Devices, J.P. Gambino, R.S. Graf, J.C. Malinowski, A.R. Cote, W.H. Guthrie, K.M. Watson, M.D.Levy, P.F. Chapman, G.A. Mason, M.D. Jaffe: IBM Microelectronics, K.K. Sims, Global Foundries, T. Aoki, IBM Research

RF devices are sensitive to noise coupling between devices. One source of coupling is the edge seal ring. We propose using a segmented guard ring to reduce coupling between devices. We demonstrate that the segmented guard ring is reliable for a 0.18 µm RF technology.


3:10PM – 5:20PM
Friday, May 23

12.1 – INVITED – Review of 3D Sequential Integration Opportunities and Technology Optimization, P. Batude, B. Sklenard, C. Fenouillet-Beranger, B. Previtali, C. Tabone, O. Rozeau, O. Billoint, O. Turkyilmaz, G. Cibrario, L. Brunet, F. Deprat, J-E. Michallet, H. Metras, C. Reita, F. Clermidy and M. Vinet, CEA-leti, Minatec, Grenoble France

Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity

12.2 – Effect of Microstructure on Via Extrusion Profile and Reliability Implication for Copper Through-Silicon Vias (TSVs) Structures, Tengfei Jiang, Chenglin Wu, Jay Im, Rui Huang and Paul S. Ho, University of Texas, Austin, TX

In this work, the effect of grain structure on TSV extru-sion and its reliability implication are investigated through experimental measurements and modeling analysis. The grain orientation, elastic anisotropy and local plasticity are found to be important in controlling the extrusion profile which can directly impact the back-end-of-line (BEOL) reliability. Re-sults from this study suggest that the Cu microstructure should be optimized from both global and local aspects in order to minimize the extrusion damage to the 3D structure.

12.3 – 2D vs 3D Integration: Architecture-Technology Co-Design for Future Mobile MPSoC Platforms, Prashant Agrawal*#, Dragomir Milojevic*$, Praveen Raghavan*, Liesbet Van der Perre*#, Francky Catthoor*#, Eric Beyne*, Ravi Varadarajan**, *IMEC, #KU Leuven, $UL Brussels, **Atrenta Inc

3D stacked ICs (3D-SIC) are viable alternatives to overcome limitations faced by mobile MPSoC platforms in 2D designs. In this paper, we evaluate 2D-IC and 3D-SIC (memory-on-logic) at system architecture level for a complex MPSoC platform instantiated for wireless PHY processing (WLAN, LTE). For a 10-core heterogeneous MPSoC instantiation, we compare its implementations as 2D-IC and 3D-SIC (based on Cu-Cu bonding), and for two different level-1 data Memory organization and communication bus structure. We also analyse impact of system level choices (memory organization, communication structure) for both 2D and 3D interconnects.

12.4 – Foundry TSV Integration and Manufacturing Challenges, S. Q. Gong, W. Liu, J. B. Tan, M. Bhatkar, H. Cong, J. Oswald, E. Lo, S. Y. Siah, GLOBALFOUNDRIES

Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.

12.5 – Impact of Die Partitioning on Reliability and Yield of 3D DRAM, Woongrae Kim, Dae-Hyun Kim, Hee Il Hong*, Linda Milor, and Sung Kyu Lim, Georgia Institute of Technology, *Samsung Electronics

In this paper we present comparative study on reliability and yield analysis of 3D SDRAM designs built with two practical die partitioning styles, namely, cell/logic-mixed and cell/logic-split. Our simulation and analysis results provide useful design tradeoffs in terms of area, TSV count, reliability, power, performance, and yield. Our studies are based on GDSII layouts and sign-off quality timing, power, and reliability analysis.