TECHNICAL PROGRAM 2017
TUESDAY, MAY 16
8:30am – 8:40am Opening
8:40am – 9:30am Plenary Session
9:50am – 12:00pm Process Integration I
12:00pm – 1:30pm Conference Luncheon
1:30 pm – 2:45pm Advanced Characterization & Modelling I
2:45pm – 3:35pm Contact
3:50pm – 6:00pm Materials & Unit Processes I
WEDNESDAY, MAY 17
8:00am – 9:20am Plenary Session
9:40am – 11:10am 3D Integration & Packaging I
11:10am – 12:00pm Reliability & Failure Analysis I
12:00pm – 1:30pm Conference Luncheon
1:30pm – 2:50pm Reliability & Failure Analysis II
3:05pm – 4:30pm Novel System & Emerging Technology
4:30pm – 6:00pm Poster Session
THURSDAY, MAY 18
8:30am – 10:15am Advanced Memory & Process Integration II
10:35am – 12:00pm 3D Integration & Packaging II
12:00pm – 1:30pm Conference Luncheon
1:30pm – 2:45pm Advanced Characterization & Modelling II
4:50pm – 5:00pm Closing Remarks/Adjourn
Opening
8:30 – 8:40 Welcome Soo-Hyun Kim, Chair 2017 IITC Conference
Session 1 Plenary Session
8:40 – 9:30 Keynote Address
Interconnect Technology opportunities to deliver user experience gains in future technologies
Chidi Chidambaram, Vice President, Qualcomm
Session 2 Process Integration I
9:50 – 12:00
2.1 Invited — A highly reliable low-k/Cu Interconnect technology for logic/memory devices,
Inhee Lee, SK Hynix Semiconductor
2.2 Reliable Airgap BEOL Technology in Advanced 48 nm Pitch Copper/ULK Interconnects for Substantial Power and Performance Benefits
C. Penny*, S. Gates, B. Peethala, J. Lee, D. Priyadarshini, S. Nguyen, P. McLaughlin, E. Liniger, C.-K. Hu, L. Clevenger, T. Hook, H. Shobha, P. Kerber, I. Seshadri, J. Chen, D. Edelstein, R. Quon, G. Bonilla, V. Paruchuri, and E. Huang
IBM Research at Albany Nanotech
2.3 N5 Technology Node Dual-Damascene Interconnects Enabled Using Multi Patterning
B. Briggs, C. J. Wilson, K. Devriendt, M. H. van der Veen, S. Decoster, S. Paolillo, J. Versluijs, E. Kesters, F. Sebaai, N. Jourdan, Z. El-Mekki, N. Heylen, P. Verdonck, Danny Wan, O. Varela Pedreira, K. Croes, S. Dutta, J. Ryckaert, A. Mallik, S. Lariviere, J. Bömmels, Zs. Tőkei
IMEC
2.4 Advance Patterning Approach for Cu/Low-k interconnects
C.H. Tsai, C. J. Lee, C.H. Huang, Jay Wu, H.W. Tien, H.C. Yao, Y.C. Wang, S. L. Shue, M. Cao
Taiwan Semiconductor ManufacturinCo., Ltd.
2.5 Planarity Considerations in the SADP Scheme for Advanced BEOL Application
James Hsueh-Chung Chen and Terry A. Spooner, IBM
Jason E. Stephens, Shao Beng Law, Genevieve Beique, Ben Kim, Martin O’Toole, Louis Lanzerotti, Steven Leibiger, E. Todd Ryan, Shreesh Narasimha, and Craig Child, GLOBALFOUNDRIES,
Session 3 Advanced Characterization & Modelling I
1:30pm – 2:45pm
3.1 Impact of Pattern Collapse on Future Micro/Nano Fabrication
Xiao Hu Liu, IBM TJ Watson Research
3.2 Modeling of Tone Inversion Process Flow for N5 Interconnect to Characterize Block Tip to Tip
S. Guissi, W. F. Clark, A. Juncker, J. Ervin*, K. Greiner*, D. Fried*, COVENTOR
B. Briggs, K. Devriendt, F. Sebaai, A. Charley, C. J. Wilson, J. Boemmels, Z. Tőkei, IMEC
3.3 Layout Based Monte-Carlo Simulation (LBMCS) for Complex Back End of Line (BEOL) Design Rule Study
Dongbing Shao*, L. A. Clevenger, Shyng-Tsong Chen, Robert Wong, IBM Semiconductor Technology Research
Session 4 Contact
2:45pm – 3:35pm
4.1 Ultralow Resistive Wrap Around Contact to Scaled FinFET Devices by using ALD-Ti Contact Metal
S-A. Chew, H. Yu2 , M. Schaekers, S. Demuynck, G. Mannaert, E. Kunnen, E. Rosseel, A. Hikavyy, A. Dangol, K. De Meyer2, D. Mocuta and N. Horiguchi, IMEC
G. Leusink, C. Wajda, T. Hakamata, T. Hasegawa, K. Tapily and R. Clark, TEL
4.2 Transistors on two-dimensional semiconductors: contact resistance limited by the contact edges
G. Arutchelvan1,2, P. Matagne1, C. Lockhart de la Rosa1,2, S.Sutar1, S. De Gendt1,2, M. Heyns 1,2, I. Radu1, 1 imec, 2 also with K.U. Leuven, Leuven, Belgium
Session 5 Materials & Unit Processes I
3:50pm – 6:00pm
5.1 Synthesis and application of Atomic Layer Deposition based 2D Transition Metal Dichalcogenides (TMDCs)
Jusang Park, Yonsei University
5.2 Ultra-thin ALD-MnN Barrier for Low Resistance Advanced Interconnect Technology
Shin-Yi Yang, Ming-Han Lee, Ching-Fu Yeh, Shih-Kang Fu, Yu-Chen Chan, Shau-Lin Shue, Min Cao, Taiwan Semiconductor Manufacturing Co, Ltd.
5.3 Metallurgical and Electrical Characterization of Ultrathin CoTix Liner/Barrier for Cu Interconnects
Maryamsadat Hosseini and Junichi Koike, Department of Materials Science, Tohoku University
5.4 Cobalt Fill for Advanced Interconnects
Nikolaos Bekiaris, Zhiyuan Wu, He Ren, Mehul Naik, Jin Hee Park, Mark Lee, Tae Hong Ha, Wenting Hou, Jonathan R. Bakke, Max Gage, You Wang, Jianshe Tang, Applied Materials, Inc.
5.5 Microstructure Modulation for Resistance Reduction in Copper Interconnects
C.-C. Yang, T. Spooner, P. McLaughlin, C.K. Hu, H. Huang, Y. Mignot, M. Ali, G. Lian, R. Quon, T. Standaert and D. Edelstein, IBM Research,
Session 6 Plenary Session
8:40 – 9:20 Keynote Address
Session 7 3D Integration & Packaging I
9:40 – 11:10
7.1 Invited — 3D Packaging Technology Platforms for the “Beyond Moore” Era
Jinho An,
7.2 Invited — Footprint-efficient and low cost monolithic 3D+ IC using backend compatible processes for IoT application
Chih-Chao Yang
7.3 Invited — Status and opportunities for sequential 3D integration
Maud Vinet
Session 8 Reliability & Failure Analysis I
11:10 – 12:00
8.1 Opportunities for Further BEOL Technology Scaling using Power-Law IMD TDDB model on 10/14nm BEOL Process Technologies and Beyond
Tae-Young Jeong, Jinseok Kim, Myungsoo Yeo, Jonghyuk Park, Miji Lee, Sari Windu, Hyunjun Choi, Yuri Choi, Yunkyung Jo, Mi-ji Lee and Sangwoo Pae, Samsung Electronics Co., Ltd.
8.2 Considering Percolation Path Growth in Low-k Dielectric TDDB Measurements
C. Wu*, Y. Li, Zs. Tőkei, and K. Croes, Imec
Session 9 Reliability & Failure Analysis II
1:30 – 2:50
9.1 Invited — Local Crystallinity-Induced Deterioration of the Lifetime of Thin-Film Interconnections
Hideo Miura
9.2 Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires
C.-K. Hu, J. Kelly, J. H-C Chen, H. Huang, Y. Ostrovski, R. Patlolla, B. Peethala, P. Adusumilli, T. Spooner, IBM
G. Lian, M. Ali, R. Long Jr, G. Hornicek, T. Kane, IBM
9.3 Study of electromigration mechanisms in 22nm half-pitch Cu interconnects by 1/f noise measurements
S. Beyne1,2, K. Croes2, M. H. van der Veen2, O. Varela Pedreira2, Q. Qi1, I. De Wolf 1,2 and Zs. Tőkei2, 1MTM, 2IMEC
Session 10 Novel System & Emerging Technology
3:05 – 4:30
10.1 Invited — Optical Interconnection and Its Device and Process Technology
Tsuyoshi Horikawa
10.2 Invited — Incoperating Graphene into Back End-of-Line for better Cu Interconnects
Ling Li
10.3 Spin waves for interconnect applications
F. Ciubotaru, O. Zografos, G. Talmelli, C. Adelmann, I.P. Radu, imec
T. Fischer, A. Chumak, P. Pirro, B. Hillebrands, University of Kaiserslautern
T. Devolder, Centre de Nanoscience et Nanotechnologie
Session 11 Posters
4:30 – 6:00
11.1 Reducing Insertion Loss of Carbon-Based Coplanar Waveguide with CVD Graphite
11.2 Segment Removal Strategy in SAQP Technology for Advanced BEOL Application
11.3 Wide Range Tuning of Titanium Nitride Sheet Resistance for Thin Film Resistors
11.4 Tungsten Corrosion and Recess Improvement by Feasible Slurry and Clean Chemical in WCMP Process
11.5 RDL layout pattern reliability analysis and optimization with TCAD stress modeling
11.6 Fabrication and Characterization of Copper Nanowires with Dense Nanoscale Twin Boundaries
11.7 Integration Challenges of Low Temperature BEOL Interconnects
11.8 Reliability of Hybrid Bond Interconnects
11.9 3D Stacking Cobalt and Nickel Microbumps and Kinetics of Corresponding IMCs at Low Temperatures
11.10 Pure Co films of low resistivity and high conformality by low temperature thermal CVD/ALD using novel Co precursors
11.11 Multiscale observations of seed layer resistance on VLSI damascene structures
11.12 Microreplicated CMP Pad for RMG and MOL Metallization
11.13 Tri-Layer Nanoindentation for Mechanical Characterization of Ultra-Low-K Dielectrics
11.14 Middle of Line RC Performance Study at the 7 nm Node
11.15 New Asymmetric Atomistic Model for the Analysis of Phase-engineered MoS2-Gold Top Contact
11.16 Growth rate of IMC in the binary sytems of Co/Sn and Cu/Sn
11.17 Feasibility study of Cu paste printing technique to fill deep via holes for low cost 3D TSV applications
11.18 Enabling porous low-k dielectric sealing against CVD Mn indiffusion in 22nm half-pitch (dual) damascene interconnects by deposition of sub-1nm thin organic films: from fun-damentals to reliability
11.19 Minimized Hysteresis and Low Parasitic Capacitance TSV with PBO (Polybenzoxazole) Liner to Achieve Ultra-High-Speed Data Transmission
11.20 Evaluation of Contact Resistivity of PtHfSi to p-Si(100) with Dopant Segregation Process
11.21 Low temperature atomic layer deposition of Ru thin films using a new carbonyl-based Ru precursor and non-oxidizing reactants; Applications to the seed layer for Cu metallization
11.22 Methodologies for Evaluating Post-Etching Damage in Ultra-low-k Dielectrics and New Chemistry for Damage Reduction
11.23 Improving the Conformality of Liner/Barrier/Seed Layers for Scaling the TSV Metallization
11.24 Identifying Wafer Fabrication Defect Signatures
Session 12 Advanced Memory & Process Integration II
8:30 – 10:15
12.1 Invited — Smart Interconnect Technology using sing Cu Atom Switch for Next Wave of Computing
Munehiro Tada
12.2 Cobalt/Copper Composite Interconnects for Line Resistance Reduction in both Fine and Wide Lines
T. Nogami, R. Patlolla, J. Kelly, B. Briggs, H. Huang, J. Demarest, J. Li, R. Hengstebeck, X. Zhang1, G. Lian, B. Peethala, P. Bhosale, J. Maniscalco, H. Shobha, S. Nguyen, P. McLaughlin, T. Standaert, D. Canaperi, D. Edelstein, and V. Paruchuri, IBM Research, 1GLOBALFOUNDRIES
12.3 Cobalt Interconnect on Same Copper Barrier Process Integration at the 7nm node
Frank W. Mont1, Xunyuan Zhang1, Wei Wang2, James J. Kelly2, Theodorus E. Standaert2, Roger Quon2, E. Todd Ryan1, 1GLOBALFOUNDRIES, 2 IBM
12.4 Feasibility Study of Fully Self Aligned Vias for 5nm Node BEOL
Gayle Murdoch, Jürgen Bömmels, Christopher J. Wilson, Khashayar Babaei Gavan, Quoc Toan Le, Zsolt Tőkei, imec
William Clark, COVENTOR
Session 13 3D Integration & Packaging II
10:35 – 12:00
13.1 Invited — Crack Resistant Interconect Structures for Advanved Packaging Solutions
Tom Shaw
13.2 Invited — An Advanced CuCu Hybrid Bonding For Novel Stacked CMOS Image Sensor
Yoshihisa Kagawa
13.3 A Novel Role for SiCN to Suppress H2O Outgas from TEOS oxide films in Hybrid Bonding
T. Ueda, M. Tetani, Y. Morinaga, M. Hamada, M. Takeuchi, K. Ichinose, S. Uya, H. Yano, N. Sato, and S. Matsumoto, TowerJazz Panasonic Semiconductor Co., Ltd.
Session 14 Advanced Characterization & Modelling II
1:30 – 2:45
14.1 Interconnect Design for Evolutionary, and Revolutionary Transistor Technologies
Divya Prasad, and Azad Naeemi, Georgia Institute of Technology
14.2 Replacing Copper Interconnects with Graphene at a 7-nm Node
Ning C. Wang1,2, Saurabh Sinha2, Brian Cline2, Chris D. English1, Greg Yeric2, Eric Pop1, 1Stanford University, 2ARM Inc.,
14.3 Resistance Contributions to Copper Interconnects
C. Witt, F. Baumann, GLOBALFOUNDRIES Research
E.Huang, D. Rath, IBM
Session 15 Materials & Unit Processes II
3:05 – 4:50
15.1 Invited — Molecular Design of Molecular Hybrids for Nano and Flexible Electronics
Reinhold Dauskardt
15.2 Methods to lower the resistivity of ruthenium interconnects at 7 nm node and beyond
Xunyuan Zhang1, Huai Huang2, Raghuveer Patlolla2, Frank W. Mont1, Xuan Lin1, Mark Raymond1, Cathy Labelle1, E. Todd Ryan1, Donald Canaperi2, Theodore E. Standaert2, Terry Spooner2, Griselda Bonilla2, Daniel Edelstein2., 1GLOBALFOUNDRIES, 2IBM
15.3 Ruthenium interconnects with 58 nm2 cross-section area using a metal-spacer process
Shibesh Dutta,1,2 Shreya Kundu,1 Lianggong Wen,1 Geraldine Jamieson,1 Kristof Croes,1 Anshul Gupta, 1imec, 2KU Leuven
15.4 Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm2
A. Pyzyna, H. Tsai, M. Lofaro, L. Gignac, H. Miyazoe, R. Bruce, C. M. Breslin, M. Brink, D. Klaus, M. Guillorn, C. Lavoie, K. P. Rodbell, D.-G. Park, E. Joseph, IBM Research