TECHNICAL PROGRAM FOR IEEE IITC 2022

Monday, June 27, 2022

Workshop – Details coming soon.

Tuesday, June 28, 2022

Session 1: Conference kick-off / Awards Program
Session 2: 3D Integration and Advanced Packaging
Session 3: 3D Integration and Advanced Packaging 2
Session 4: Memory and Emerging Technologies

Wednesday, June 29, 2022

Session 5: Reliability
Session 6: Unit Process and Integration
Session 7: Unit Process and Integration
Session 8: Advanced Interconnects
Poster Session : Conference Reception

Thursday, June 30, 2022

Session 9: Advanced Interconnects
Session 10: DTCO
Session 11: DTCO and Unit Process and Integration

**All times in pacific standard time.

Tuesday, June 28, 2022

Session 1: Conference Kick-off and Awards Program

8:15 – 8:25
Welcome
Hui Jae Yoo – AMAT

8:25 – 8:35
Award Program – Best Papers 2021

8:35 – 9:25
Keynote – Directions, Challenges and Opportunities in Heterogeneous Integration
Ravi Mahajan – Intel

view abstract

9:25 – 10:15
Keynote – EUV lithography: what’s up and what’s next
Anthony Yen – ASML

view abstract

10:15 – 10:35 Coffee Break

Session 2: 3D Integration and Advanced Packaging

10:35 – 11:05
2.1 Heterogeneous Integration for AI Architectures
Invited – Mukta Farooq, IBM Research

11:05 – 11:35
2.2 Ponte Vecchio : Building a Foundation to Enable 1000X Scaling for the Third Dimension of Moore’s Law
Invited – Wilfred Gomes, Intel Corporation

11:35 – 12:00
2.3 Pixel Pitch Hybrid Bonding and Three Layer Stacking Technology for BSI Image Sensor
Kazumasa Tanida*, Shigeru Suzuki, Toshiki Seo, Yasunori Morinaga, Hayato Korogi, Michinari Tetani, Masakazu Hamada, Ryuji Eto, Takeshi Yamashita, Yasuhiro Kato, Naoaki Sato, Tadami Shimizu, Tetsuro Hanawa, Hiroko Kubo, Kenji Ueda, Fumitaka Ito, Yoshihiro Noguchi, Masayuki Nakamura, Ryuji Mizukoshi, Masahiko Takeuchi, Masakatsu Suzuki, Naoto Niisoe, Isao Miyanaga, Atsushi Ikeda, Susumu Matsumoto, Tower Partners Semiconductor

12:00 – 13:20 Lunch

Session 3: 3D Integration and Advanced Packaging

13:20 – 13:50
3.1 Cu Hybrid Bonding Process Key Challenges and Solutions to C2W and W2W Bonding Applications
Invited –
Wei Zhou, Micron

13:50 – 14:20
3.2 Nanoengineered CTE Tailorable Copper Solder for Robust High Performance Heterogeneous Integration and Packaging
Invited –
Alfred Zinn, Kuprion Inc

14:20 – 14:45
3.3 TSV fabrication technology using direct electroplating of Cu on the electroless plated barrier metal
Shoso Shingubara*, Tomohiro Shimizu, Kosuke matsui, yuko miyake, Yuichiro Torinari, Makoto Motoyoshi, Shigeru Watariguchi, Hideki Watanabe, Kansai Univ

14:45 – 15:05 pm Break

Session 4: Memory and Emerging Technologies

15:05 – 15:35
4.1 A Materials to Systems Understanding of a BEOL Embedded Analog NVM Memory Technology for Edge Compute Applications
Invited – 
Michael Chudzik, AMAT

15:35 – 16:05
4.2 Demonstration of HfO2-based BEOL-integrated ferroelectric memories: current status and future challenges
Invited – 
Laurent Grenouillet, CEA-Leti

16:05 – 16:35
4.3 Via-switch FPGA with Transistor-free Programmability
Invited – 
Masanori Hashimoto, Kyoto University

16:35 – 17:00
4.4 Carbon Plug Application in 3D NAND Fabrication
Yu Chih Chang, Liang-Yu Chen, Kuang-Wei Chen*, Tuung Luoh, Ling-Wuu Yang, Ta-Hone Yang, Kuang-Chao Chen, Macronix

17:00 – 17:25
4.5 Low Temperature 90nm Pitch Invertigations for BEOL Quantum Applications
Roselyne Segaud, Patrice Gergaud, Stephane Minoret, Paul Neuman, Frederic Gustavo, Agnes Royer, Christophe Licitra, Denis Mariol, Fatrice Nemouchi, CEA-Leti

Wednesday, June 29, 2022

Session 5: Reliability

8:15 – 8:40
5.1 Effects of composition deviation of CuAl2 on Electromigration
Toshihiro Kuge, Masataka Yahagi, Junichi KoikeToshihiro Kuge, Masataka Yahagi, Junichi Koike, Tohoku Univ

8:40 – 9:05
5.2 Dynamics of electromigration voids in Cu interconnects: investigation using a physics-based model augmented by neural networks
 (Student) Ahmed S. Saleh, Houman Zahedmanesh, Hajdin Ceric, Kristof Croes, Ingrid De Wolf, IMEC

9:05 – 9:30
5.3 Reliability Evaluation of Semi-damascene Ru/Air-Gap interconnect with Metal Pitch down to 18 nm
Alicja Lesniewska, Olalla Varela Pedreira, Philippe Roussel, Giulio Marti, Ankit Pokhrel, Marleen H. van der Veen, Stefan Decoster, Martin O’Toole, Gayle Murdoch, Ivan Ciofi, Seongho Park, Zsolt kei, Kristof Croes, IMEC

9:30 – 9:55
5.4 Reliability benchmark of various via prefill metals
Olalla Varela Pedreira, Veerle Simons, Marleen H. van der Veen, Ivan Ciofi, Seongho Park, Zsolt Tokei, Kristof Croes, Shirish Pethe, Wei Lei, Shinjae Hwang, Zhiyuan Wu, Feng Chen, Alexander Jansen, Jerome Machillot, Andrew Cockburn, IMEC

9:55 – 10:20
5.5 Failure Mode Analysis in Microsecond UV Laser Annealing of Cu Thin Films
Remi Demoulin, Richard Daubriac, Louis Thuries, Emmanuel Scheid, Fabien Rozé, Fuccio Cristiano, Toshiyuki Tabata, Fulvio Mazzamuto, Laser Systems & Solutions of Europe (LASSE)

10:20 – 10:40 AM Break

Session 6: Unit Process and Integration

10:40 – 11:10
6.1 Recent Progress in Graphene Processes for Metallization and RF Applications
Invited – Kazuyoshi Ueno, Shibaura Institute of Technology

11:10 – 11:40
6.2 Advanced process technologies for continuous logic scaling towards 2nm node and beyond
Invited – Tomonari Yamamoto, Tokyo Electron Limited

11:40 – 12:05
6.3 Computational Analysis of the Role of Nanoconfinement on the Reliability of ULK Glasses
Karsu Kilic, Reinhold Dauskardt, Stanford

12:05 – 13:25 Lunch

Session 7: Unit Process and Integration

13:25 – 13:50
7.1 Improvement of Line-to-line TDDB by Cu and Barrier-metal Recess Structure for high voltage circuit in 3D Flash Memory
Mitsuhiko Noda, Kotaro Fujii, Naomi Yanai, Tsubasa Watanabe, Atsushi Kato, Kosuke Horibe, Eiru Yoshida, Tatsuhiko Koide, Hiroshi Fujita, Yumi Nakajima, Masayoshi Tagami, Kazuya Ohuchi, Kioxia

13:50 – 14:15
7.2 Enabling 3-level High Aspect Ratio Supervias for 3nm nodes and below
Daniel Montero, Victor Vega Gonzalez, Yannick Feurprier, Olalla Varela Pedreira, Noriaki Oikawa, GERARDO Martinez, Dmitry Batuk, Harinarayanan Puliyalil, Janko Versluijs, Hanne De Coster, Nina Bazzazian, Nicolas Jourdan, Kaushik Kumar, Frederic Lazzarino, Gayle Murdoch, Seongho Park, Zsolt Tokei, IMCE

14:15 – 14:40
7.3 Galvanic Corrosion Effect of Co Liner on ALD TaN Barrier
Junki Jang, Changhyun Kim, Youngsoo Yoon, Yun Ki Choi, Hoon Kim, Jungil Park, Jaehyeong Park, Minguk Kang, Youngwoo Kim, Seonguk Jang, Junghwan Ahn, Eunyoung Park, Wonmin Jeong, Jeongjae Kim, Minhyuk Oh, Wonkyu Han, Dongwoo Shin, Wookhwan Kim, Jaeyoung Yang, Honglae Park, Segab Kwon, Jeong Hoon Ahn, Dr. Ku, Jahum, Samsung

14:40 – 15:00 PM Break

Session 8: Advanced Interconnects

15:00 – 15:30
8.1 A Advanced interconnect technology for 2nm node and beyond
Invited – 
Jinnam Kimm, Samsung Electronics

15:30 – 15:55
8.2 Metal-Induced Line Width Variability Challenge and Mitigation Strategy in Advanced Post-Cu Interconnects
Koichi Motoyama, Nick Lanzillo, Sagarika Mukesh, Cornelius Brown Peethala, Terry Spooner, daniel edelstein, Kisik Choi, IBM

15:55 – 16:20
8.3 Barrierless ALD Molybdenum for Buried Power Rail and Via-to-Buried Power Rail metallization
Anshul Gupta, Jan Willem Maes, Nicolas Jourdan, Chiyu Zhu, Sukanya Datta, Olalla Varela Pedreira, Quoc Toan Le, Dunja Radisic, nancy heylen, Antoine Pacco, Shouhua Wang, Moataz Mousa, Young Byun, Felix Seidel, Bart de Wachter, Gayle Murdoch, Zsolt Tokei, Eugenio Dentoni Litta, Naoto Horiguchi, IMEC

16:20 – 16:45
8.4 MP18-26 Ru Direct-Etch Integration Development with Leakage Improvement and Increased Aspect Ratio
Ankit Pokhrel, Giulio Marti, Martin O’Toole, Gayle Murdoch, Anshul Gupta, Stefan Decoster, Souvik Kundu, Elisabeth Camerotto, Quoc Toan Le, Arame Thiam, Alicja Lesniewska, Seongho Park, Zsolt Tokei, IMEC

16:45 – 17:10
8.5 Balancing Interconnect Resistance and Capacitance at the Advanced Technology Nodes based on Full Chip Analysis
(Student) Da Eun Shim, Azad Naeemi, GIT

17:30 – 19:30
Poster Session – Conference Reception

Thursday, June 30, 2022

Session 9: Advanced Interconnects

8:15 – 8:45
9.1 Recent Advances in Ni-based GeSn Metallization
Invited – Philippe Rodriguez, CEA-Leti

8:45 – 9:15
9.2 ALD of Ru with bulk-like resistivity by balancing precursor concentration to maximum surface mobility and minimize contaminants
Invited – 
Andy Kummel, UCSD

9:15 – 9:40
9.3 Capacitive Impacts of Etch-Induced Dielectric Damage in Highly-Scaled Interconnect Architectures
Janet M Wilson, Nick Lanzillo, IBM

9:40 – 10:05
9.4 Performance improvement for Cu interconnects by SAM and ELD technologies
Yuki Kikuchi, Tokyo Electron Limited

10:05 – 10:30
9.5 Low Resistance Cu Vias for 24nm Pitch and Beyond
Marleen H. van der Veen, Olalla Varela Pedreira, Nicolas Jourdan, Seongho Park, Herbert Struyf, Zsolt Tokei, Carmen Leal Cervantes, Feng Chen, Xiangjin Xie, Zhiyuan Wu, Alexander Jansen, Jerome Machillot, Andrew Cockburn, IMEC

10:30 – 10:50 AM Break

Session 10: DTCO

10:50 – 11:20
10.1 Design-Technology Co-Optimization for BEOL Interconnect in Advanced Technologies
Invited – Pieter Woltgens, ASML

11:20 – 11:45
10.2 EUV Minimum Pitch Single Patterning for 5nm Node Manufacturing
Jungil Park, Yun Ki Choi, Jeong Hoon Ahn, Byung Je Jung, Hoyoun Lee, Jinho Kim, Eunyoung Park, Jaehyeong Park, Hyun-Ji Song, Miji Lee, Dr. Ku, Jahum, Samsung

11:45 – 12:10
10.3 Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis
Anita Farokhnejad, Simone Esposto, Ivan Ciofi, Odysseas Zografos, Pieter Weckx, Julien Ryckaert, Pieter Schuddinck, Yang Xiang, Zsolt Tokei, IMEC

12:10 – 13:30 Lunch

Session 11: DTCO and Unit Process and Integration

13:30 – 13:55
11.1 Cryogenic CMOS Performance Analysis Including BEOL Characteristics at 4K for Quantum Controller Application
Koichiro Okamoto, Takahisa Tanaka, Makoto Miyamura, Hiroki Ishikuro, Ken Uchida, Toshitsugu Sakamoto, Munehiro Tada (Recording), NanoBridge Semiconductor

13:55 – 14:20
11.2 Dual Damascene 28nm-Pitch Single Exposure EUV Design Rules Evaluation by Voltage Contrast Characterization
Victor M. Carballo, Dorin Cerbu, Filip Schleicher, Jeroen van de kerkhove, Philippe Leray, Nicola Kissoon, Etienne De Poortere, IMCE

14:20 – 14:50
11.3 Death No Moore: EUV Dry Resist for Continuous Scaling of Semiconductor Devices
Invited – 
Qinghuang Lin, Lam Research

14:50 – 15:20
11.4 Unit Process Trends and Challenges for Advanced Interconnect Scaling
Invited – 
Andy Simon, IBM Research

15:20 – 15:45
11.5 ALD Mo for Advanced MOL Local Interconnects
Maryamsadat Hosseini, Davide Tierno, Jan Willem Maes, Chiyu Zhu, Sukanya Datta, Young Byun, Moataz Mousa, Nicolas Jourdan, Eugenio Dentoni Litta, Naoto Horiguchi, IMEC

15:45 – 16:10
11.6 Low Resistivity Tungsten and Ruthenium through Textural Control Using Ion Beam Deposition
Rutvik Mehta, Frank Cerio, Yuejing (Crystal) Wang, Paul Turner, Jinho Kim, Ashish Kulkarni, Mohammad Saghayezhian, Robert Caldwell, VEECO