Please register in the conference area as soon as possible after arrival during the opening times:
Sunday 21st: 7:30 pm – 9:00 pm
Monday 22nd: 8:00 am – 5:30 pm
Tuesday 23rd: 7:00 am – 5:00 pm
Wednesday 24th: 7:30 am — 6:00 pm
Thursday 25th: 7:30 am – 4:30 pm
Program
TECHNICAL PROGRAM FOR IEEE IITC 2023
Monday, May 22, 2023
WORKSHOP:
- Non-volatile memory-based artificial synaptic devices for neuromorphic computing
- Embedded NVM for AI – Which memory is going to make the race?
- Si photonics for optical interconnects
- Enabling Technologies for CMOS near fabrication of next generation devices – A research Fab perspective
- Interconnects for 3D integration of quantum technologies
- Quantum computing using NV centers
- Workshop, Keynote and Invited Speaker & Committee Reception
Tuesday, May 23, 2023
Session 1: Conference kick off and awards ceremony
Session 2: 3D/2.5D Integration/Packaging
Session 3: Advanced Interconnects I
Wednesday, May 24, 2023
Session 4: Interconnects and BEOL Elements for Memory
Session 5: Contacts to MOS Devices: Silicide, III-V, 2D Materials
Session 6: Design-Technology Co-optimization
Session 7: Modelling
Session 8: Materials and Unit Process
Thursday, May 25, 2023
Session 9: Reliability and Failure Analysis
Session 10: Novel System and Emerging Technology
Session 11: Metrology
Session 12: Advanced Interconnect II
**All times in Central European Time (CET)
Tuesday, May 23, 2023
Session 1: Conference kick off and awards ceremony
8:15 – 8:30
Welcome
Stefan Schulz, TU Chemnitz / Fraunhofer ENAS
8:30 – 8:40
Award ceremony
8:40 – 9:20
Keynote – From Microns to Nanometers: Overcoming the Challenges of Scaling Interconnects
Sundar Ramamurthy, Applied Materials
9:20 – 10:00
Keynote – Scaling CMOS Technology beyond Nanometers
Ken Rim, SAMSUNG
10:00 – 10:25 Coffee Break
Session 2: 3D/2.5D Integration/Packaging
10:25 – 10:55
2.1 7 Years after the A10 Processor, the Era of Heterogeneous Integration
Invited – WoongSun Lee, SK HYNIX
10:55 – 11:15
2.2 Development of 3-layer stacked global shutter CMOS image sensor with pixel pitch Cu-to-Cu interconnection and high-capacity capacitors
Seungjae Oh, SAMSUNG
11:15 – 11:35
2.3 Development of copper µbumps based flip chip assembly for heterogeneous photonic integration
Juliette Auffret, Univ.Grenoble Alpes, CEA, Leti
11:35 – 13:20 Lunch
Session 3: Advanced Interconnects I
13:00 – 13:30
3.1 Airgap Integration on Patterned Metal Lines for Advanced Interconnect Performance Scaling
Invited – Hsiao Kang Chang, TSMC
13:30 – 13:50
3.2 Improving uniformity of 3-level High Aspect Ratio Supervias
Daniel Montero, IMEC
13:50 – 14:10
3.3 A novel integration scheme for self-aligend Ru topvia as post-Cu alternative metal interconnects
Koichi Motoyama, IBM
14:10 – 14:30
A Study of Resistivity Control for Subtractive Interconnects Using Ruthenium
Jack Rogers, TEL Technology Center, America, LLC
14:30 – 14:50
Two-level Semi-damascene interconnect with fully self-aligned vias at MP18
Giulio Marti, IMEC
Poster Session
14:50 – 17:00 – Poster Session & coffee break
P1. Fabrication of local areas with high aspect ratio silicon structures using MACE
Mathias Franz, Fraunhofer ENAS
P2. Galvanic displacement deposition of Ag using citric acid for Cu-to-Cu hybrid bonding
Youjung Kim, Hanyang University
P3. Cu-SiO2 Surface Activation by Ozone-Ethylene-Radical Process for Chip-to-Chip and Chip-to-Wafer Hybrid Bonding
Murugesan Mariappan, Tohoku University
P4. Surface Topography Control on Cu Pad for Hybrid Bonding
Kohei Nakayama, Yokohama National University
P5. The Second Generation of Integrated Stack Capacitor (ISC) for Power Integrity Improvement
Won Ji Park, Samsung Electronics
P6. Ruthenium and Rhodium Vertical Interconnect Formation Using Gas Phase Electrodeposition
Mohammad Mobassar Hossain, Technische Universität Ilmenau
P7. Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device
Junki Jang, Samsung Electronics
P8. CuAl intermetallic compound for Cu alternative
Toshihiro Kuge, Tohoku University
P9. Microsecond UV laser annealing annihilating Ru grains smaller than electron mean free path
Lu Lu, Laser Systems & Solutions of Europe (LASSE)
P10. The Formation of Ru/ZnO Multifunctional Bilayer through Area Selective Atomic Layer Deposition for Advanced Cu Metallization
Yuki Mori, TANAKA Precious Metals
P11. Evaluation of Reactive Sputtered Ti-group MAX Alloy with Different A Elements for Wiring Material
Takeyasu Saito, Osaka Metropolitan University
P12. Comprehensive Bath Monitoring of Ruthenium Wet Deposition and Etching Processes
Jingjing Wang, KLA Corporation
P13. Influence of Carbon Ion Implantation on Co Silicide Formation
Yanping He, Institute of Microelectronics Chinese Academy of Sciences
P14. Semimetallic Atomic Layer Deposited TiS2 Thin Films for Contact Resistance Improvement of MoS2-based Thin Film Transistor
Hwi Yoon, Yonsei University
P15. In situ Post Etch Treatment on Ge-rich GST after etching in HBr-based plasma
Christelle Boixaderas, Univ.Grenoble Alpes
P16. Area-Selective Atomic Layer Deposition of Ruthenium Thin Films by Chemo-Selective Adsorption of Short Alkylating Agents
Jeong-Min Lee,. Hanyang University
P17. Atomic-scale Crystal Phase Transformation of Atomic Layer Deposited Antimony Telluride Thin Films with Substrate-dependent Orientations
Sangyoon Lee, Yonsei University
P18. Area-Selective Atomic Layer Deposition of Ruthenium Thin Films Using Aldehyde Inhibitors
Haneul Park, Hanyang university
P19. Measuring Ion Energy Distribution by Retarding Field Energy Analyzer and Using Low-Energy Ions for Si-ALE by Cl2
Nils Dittmar, Fraunhofer ENAS
P20. 3D Thin Film Metrology without Cross-Sectional Sampling
Anish Philip, Chipmetrics
P21. Influence of Annealing on Microstructure of Electroplated Copper Trenches in Back-End-Of-Line
Prashant Kumar Singh, Globalfoundries
P22. Reaction-diffusion model for hydrogen release from PECVD silicon nitride film
Prafullkrishna Dani, Robert Bosch GmbH
P23. Modeling a Wet Wafer Surface Processing Chain
Max Huber, Fraunhofer ENAS
P24. Multi-scale simulation of epitaxial processes
Linda Jäckel, Fraunhofer ENAS
P25. Ultrascaled graphene-capped interconnects: a quantum mechanical study
Peter Reyntjens, imec
P26. Changing the Face of Phase Change Memory with Sb₂Te₃/TiTe₂ Superlattices
Seppe Van Dyck, Ghent University
P27. Optical high-resolution image-based defect inspection on compound semiconductors
Thomas Trautzsch, Confovis
P28. Electromigration-induced local dewetting in Cu films
Yaqian Zhang, Delft University of Technology
17:10
Guided City Tour
19:00
Dinner at: Pulverturm
Wednesday, May 24, 2023
8:20 – 8:30
House keeping
Session 4: Interconnects and BEOL Elements for Memory
8:30 – 9:00
4.1 BEoL-integrated ferroelectric RAM for advanced semiconductor technology nodes
Invited – Stefan Müller, FMC
9:00 – 9:20
4.2 A Ferroelectric BEoL Module: Adding Non-Volatile Memories and Varactors to Existing Technology Nodes
Konrad Seidel, Fraunhofer IPMS
9:20 – 9:40
4.3 TaN Thin Film Study for Superconducting BEOL Integration
Roselyne Segaud, Université Grenoble Alpes, CEA-LETI
Session 5: Contacts to MOS Devices: Silicide, III-V, 2D Materials
9:40 – 10:00
5.1 Schottky barrier height and contact resistivity reduction of metal/GaOx/n-GaN structure
Jiro Koba, Tohoku University
10:00 – 10:20
5.2 Impact of pre-amorphization implantation schemes using beam line or plasma ion implantation on Ni(Pt)Si/Si specific contact resistivities
Sophie Guillemin, Université Grenoble Alpes, CEA, LETI
10:20 – 10:45 Coffee Break
Session 6: Design-Technology Co-optimization
10:45 – 11:15
6.1 Beyond Optical Scaling – Roles and Opportunities for DTCO in Angstrom-Scale Era
Invited – Byung-Sung Kim, SAMSUNG
11:15 – 11:45
6.2 New architectures/Roadmap/ Technology/Mobile/Logic roadmap
Invited – Seung-Chul Song, GOOGLE
11:45 – 12:05
6.3 Signal-Power Interconnect Co-design based on various Technology Options
Da Eun Shim, Georgia Institute of Technology
12:05 – 13:30 Lunch / Committee Meeting
Session 7: Modelling
13:30 – 14:00
7.1 Towards Knowledge Enhanced Process Models for Semiconductor Fabrication
Invited – Jörg Schuster, Fraunhofer ENAS
14:00 – 14:20
7.2 Calibrated fast thermal calculation and experimental characterization of advanced BEOL stacks
Xinyue Chang, KU Leuven, IMEC
14:20 – 14:40
7.3 Analysis of Material, Design & LER of Advanced BEOL Metal Lines Using Process Modeling
Daebin Yim, Lam Research GK , Japan
14:40 – 15:00
Film growth from particle raytracing: A simulation method for vapor deposition processes with changing surface topographies
Erik E. Lorenz, Fraunhofer ENAS
15:00 – 15:25 Coffee Break
Session 8: Materials and Unit Process
15:25 – 15:55
8.1 Intermetallic Compounds as Alternatives to Copper for Advanced Interconnect Metallization
Invited Christoph Adelmann, IMEC
15:55 – 16:15
8.2 Reduced resistivity of NiAl by backthinning for advanced interconnect metallization
Jean-Philippe Souile, IMEC
16:15 – 16:35
8.3 An industrially compatible process for the fabrication of superconducting monocrystalline Si films
Paul Dumas, CEA-Leti
16:35 – 16:55
8.4 Graphene Cap Formation on Nickel Thin Films by Thermal CVD at Low Temperature
Kazuyoshi Ueno, Shibaura Institute of Technology
16:55 – 17:15
8.5 Atomic layer etching of molybdenum with fluorination and ion bombardment
Yongjae Kim, Sungkyunkwan University
17:15 – 17:35
8.6 Reverse Templating Effects of Low-Resistivity Ru ALD on Sputtered Ru
Victor Wang, University of California, San Diego
19:00 – 22:00 Conference dinner
Thursday, May 25, 2023
8:20 – 8:30 House keeping
Session 9: Reliability and Failure Analysis
8:30 – 9:00
9.1 Recent Advances on Qualification and Reliability of Cu/SiO2 to Cu/SiO2 Hybrid Bonds for 3D Integrated Circuits
Invited – Stéphane Moreau, CEA LETI
9:00 – 9:20
9.2 Experimental Study Of Interface & Bulk Defectivity In Ultra-Thin BEOL Dielectrics By Using Low Frequency Noise Spectroscopy
Nishant Saini, IMEC, KU Leuven
9:20 – 9:40
9.3 Advanced Electron Energy Loss Spectroscopy investigation of microelectronics devices.
Jean-Gabriel Mattei, STMicroelectronics
Session 10: Novel System and Emerging Technology
9:40 – 10:10
10.1 Stress-configurable 1D/2D Nanodevices on Waferlevel
Invited – Sascha Hermann, Chemnitz University of Technology
10:10 – 10:30
10.2 Exploring the Benefits of Cryogenic Temperatures for Co and Ru Metallizations
Davide Tierno, IMEC
10:30 – 10:55 Coffee Break
10:55 – 11:25
10.3 Solution-processable molecular oxides for integrated memories
Invited – Kirill Monakhov, Leibniz Institute of Surface Engineering (IOM)
11:25 – 11:45
10.4 3D Integration for Modular Quantum Computer based on Diamond Spin Qubits
Ryoichi Ishihara, QuTech, Delft University of Technology
Session 11: Metrology
11:45 – 12:15
11.1 Mechanical BEoL Robustness Evaluation Using Variable Loading Strategies and Acoustic Emission Damage Monitoring
Invited – André Clausner, Fraunhofer IKTS
12:15 – 12:35
11.2 Automatic Detection of Via Arrays in AFM Images for CMP Dishing Evaluation
Andreas Zienert, Fraunhofer ENAS
12:35 – 12:55
11.3 A simple analytical model to describe time-resolved concentrations of plasma species
Micha Haase, Fraunhofer ENAS
12:55 – 14:20 Lunch
Session 12: Advanced Interconnect II
14:20 – 14:40
12.1 Selective ALD Mo Deposition in 10nm Contacts
Invited
Marleen van der Veen, IMEC
14:40 – 15:00
12.2 Pre-treatment study for barrier-less Ruthenium filling into single damascene via of sub 20nm hole size
Ryota Yonezawa, TEL Technology Center, America, LLC
15:00 – 15:20
12.3 Integrating 8nm Self-Aligned Tip-to-Tip to Enable 4-track Standard Cell Architecture as Scaling Booster
Phillippe Marien, IMEC
15:20 – 15:40
12.4 Advanced BEOL process integration for logic technology nodes
Chanhoo Park, SAMSUNG
15:40 – 16:00
12.5 Towards Enabling Two Metal Level Semi-Damascene Interconnects for Superconducting Digital Logic: Fabrication, Characterization and Electrical Measurements of Superconducting NbxTi(1-x)N
Ankit Pokhrel, IMEC
16:00 – 16:15
Closing remarks
Stefan Schulz