2026 IITC Conference Program

MONDAY, JUNE 1, 2026

2026 IITC Workshop Program
Thermal Management, Materials and Design

TUESDAY, JUNE 2, 2026

Session 1: Intro/2025 Awards & Day 1 Keynote
Chair: Mansour Moinpour

8:15~8:20
Welcome
Mansour Moinpour, Conference Chair
Nick Lanzillo, Conference Co-Chair
Mark Zaleski, Program Chair

8:20 – 8:35
Award Program – Best Papers 2025

8:35 – 9:25
Keynote – Connecting the Smallest Devices, Creating the Great Impact: The Rise of Interconnects
Myung-Hee Na – Intel

9:25 – 9:45 Coffee Break

Session 2: Advanced Interconnects I
Chair: TBD

9:45 – 10:10
2.1 TBD
TBD

10:10 – 10:35
2.2 Toward Fine Pitch Superconducting Interconnects with Nb-Nb Direct Bonding [Invited]
Candice Thomas, CEA-Leti

10:35 – 10:55
2.3 Demonstration of First 16 nm Pitch Ru Topvia Interconnect through Process Optimization
Koichi Motoyama, Chris Penny, Darsith Jayachandran, Gwangsik Kim, John Kim, Joongsuk Oh, Jaemyung Choi, Nicholas Lanzillo, Belle Antonovich, Nicholas Latham, Wai Kin Li, Shravana Katakam, Harsimran Singh, Emiko Motoyama, Matt Malley, Wei-Tsu Tseng, Su-Chen Fan, Tenko Yamashita, Kang-ill Seo, Kisik Choi, Dechao Guo – IBM
We report the first demonstration of a 16 nm pitch fully subtractive Ru Topvia interconnect, with both structural integrity and electrical performance experimentally verified. High aspect ratio Ru line etching, via pillar mask formation, and Topvia reveal CMP were identified as the key yield-limiting processes and were systematically optimized. The resulting process integration scheme provides a viable fabrication pathway for post-Cu alternative metal interconnects in future advanced technology nodes.

10:55 – 11:15
2.4 Interconnect Stack Using Direct Print EUV Patterning and PowerVia for Intel 18A High Volume Manufacturing
Mehmet Koker Aykol, Mark Armstrong, Michael Asoro, Balijeet Bains, KUMHYO BYON, Ervin Hill, Vishal Javvaji, Christophe Juncker, Steven Kirby, Damian Lawrence, Gokul Malyavanatham, Bozidar Marinkovic, Diana Ivonne Paredes, Jessica Parker, Reken patel, Conor Puls, Ajay Sathe, Jared Stoeger, SHU ZHOU, Abhishek Bang, AMIT CHUGH, Ebubekir Dogan, Ramanan Ehamparam, Angel Esperanzate, Pranav Garg, Neena Gilda, Szutung Hu, Steven Richard Jim, Assad Ullah Khan, Tugba Koker Aykol, Hiten Kothari, Praveen Kumar, Wai-Yip Lo, Abdullah Al Mamun, Andrew Moore, Kari J. Moses, Pran Paul, Ashok Rajamani, Alvin Horatio Romang, Hassana Samassekou, Biswajit Sarkar, Nicole Shaver, Chung-Yu Shih, Chad Staus, Tejas Umale, Mohan Yadav, Zhenjun Zhang – Intel Corporation
This paper describes Intel’s 18A modular interconnect stack featuring PowerVia and EUV Direct Print patterned layers utilizing uni-directional dry etch process. With PowerVia technology, Intel 18A delivers optimized backside interconnects (BSIC) for low resistance power delivery and frontside interconnects (FSIC) for high-speed signal transmission.

Session 3: Contacts to CMOS Devices & Novel/Emerging Technologies I

11:15 – 11:40
3.1 Photonic Interconnects [Invited]
Voker Soger, University of Florida

11:40 – 12:00
3.2 Molybdenum Contacts for 1.4nm Technology Node and Beyond
Gaurav Thareja – Applied Materials
We present novel Middle-Of-Line (MOL) molybdenum (moly) contact integration for advanced logic technology nodes using selective moly metal deposition, and chemical mechanical planarization (CMP). Electrical tests, in-line metrology and circuit simulations confirm significant Power-Performance-Area (PPA) gains for 1.4 nm technology node and beyond

12:00 – 12:20
3.3 Extending the scaling and performance potential of BEOL Superconducting NbTiN interconnects
Benjamin Huet, Ankit Pokhrel, Gilles Delie, Nunzio Buccheri, Adham Elshaer, Daniel Perez Lozano, Sarkar Sujan Kumar, Zhang Luke, Ravi Tiwari, Seifallah Ibrahim, Blake Hodges, Julian Gil Pinzon, Peter Koufalis, Terry Kim, Oleksandr Hryhorenko, Trent Josephsen, Sabine O’Neal, Anne-marie Valente, Zsolt Tokei, Richard Rouse – Imec
In this work, we demonstrate significant downscaling of BEOL superconducting (SC) interconnects based on NbTiN, pushing both dimensional and performance limits. NbTiN nanowires with a thickness of 50 nm and critical dimensions (CD) down to 30 nm were fabricated using a CMOS BEOL-compatible process flow using 193i lithography on 300mm Si wafers. Despite extreme scaling for 193i, the interconnects exhibit robust SC behavior with well-defined critical temperatures (>12K) and a critical current density (Jc) of up to ~200 mA/µm². These results highlight the scaling potential and exceptional current-carrying capability of NbTiN, underscoring its potential as an interconnect technology for industrial superconducting computing systems.

12:20 – 12:40
3.4 Process Optimization for CFET Middle Of Line Connectivity
Assawer Soussou, Juergen Boemmels, Naoto Horiguchi, Benjamin Vincent – Lam Research Corporation
This work presents a process optimization study for CFET MOL (Middle of Line) connectivity. Backside (BS) versus frontside (FS) MOL connectivity was explored and benchmarked to evaluate the most robust options for CFET structures. A process sensitivity analysis was performed to simulate process variability impact on the geometry critical dimensions (CD) and via resistance values. The overall success rate was calculated for different CDs as well as different via resistances and compared for both MOL options. The simulation identified process parameters and corresponding process windows that need to be controlled to avoid via opens and ensure CFET MOL process manufacturability.

Lunch Break
12:20 – 1:35

Session 4: 3D Integration & Packaging I
Chair: TBD

1:35 – 2:00
4.1 Electrodeposition for Advanced Packaging: Scaling Interconnects for Future Nodes [Invited]
Stephen Banik, Lam Research

2:00 – 2:25
4.2 AI-Enabled Design and Optimization Framework for Advanced Semiconductor Packaging [Invited]
Chi-Hua Yu, National Cheng Kung University

2:25 – 2:45
4.3 Correction strategies for global and local bonding distortion in wafer backside 3D applications
Victor M. Blanco Carballo, Alex hsu, Vincent Renaud, Rami Chukka, Arup Saha, Cyrus Tabery, Etienne De Poortere, Idan Raiter, Itay davidovitch, Gorhad Kujan, Ofir Sharoni – Imec
For over 50 years, the semiconductor industry has adhered to Moore’s Law, driving an increase in chip density with each new node. While traditional 2D pitch scaling is expected to continue due to advances in materials, processes, and lithography tools, new 3D heterogeneous integration schemes have emerged, offering significant advantages in terms of power, performance, area, and cost reductions for both logic and memory applications. Wafer-to-wafer bonding has been proposed for backside power delivery and hybrid bonding applications, as it allows for tighter overlay control5 when compared with current performance of chip-to-wafer bonding. Furthermore, standard CMOS full-wafer processing can be applied, resulting in lower defectivity. However, for the successful implementation of this process, achieving tight backside and hybrid bonding overlay is essential, requiring a comprehensive understanding and control of the influencing parameters and corrections mechanisms In this work, we have developed a four-layer short loop process to investigate the effect of the bonding process, pattern density and process stress on bonding distortion, which is challenging the wafer backside overlay performance. Scanner metrology is employed to characterize the wafer distortion induced by the bonding and thinning processes. Different strategies are proposed to mitigate global distortion such as feedforward implementation and local distortion such as stress control, reticle wafer correction and laser treatment.

2:45 – 3:05
4.4 An Energy-Efficient Hierarchical RDL Interposer Architecture for AI Packages Using UCIe and PCIe Interconnects
SATORU KURAMOCHI, MASAYA TANAKA – Dai Nippon Printing Co., ltd
The rapid scaling of AI accelerators has led to a substantial increase in interconnect energy consumption within advanced packages, driven by the coexistence of ultra-high-bandwidth short-reach links and high-speed medium-reach I/O links. To address this challenge, this paper proposes an energy-efficient hierarchical RDL interposer architecture that maps interconnect standards to communication distance and bandwidth requirements, thereby optimizing interconnect energy consumption at the system level. In the proposed architecture, fine-pitch redistribution layers (RDLs) based on the UCIe standard are employed for short-reach XPU-HBM communication, achieving an interconnect energy efficiency of ~0.3 pJ/bit, while maintaining ultra-high wiring density. For medium-reach communication between AI modules and co-packaged optics (CPO), PCIe SerDes-based interconnects implemented on coarse RDL structures are utilized to ensure robust signal integrity at high data rates with an energy efficiency of ~7 pJ/bit. To demonstrate the feasibility of the hierarchical approach, a fine-pitch UCIe RDL structure incorporating a novel inorganic coating is developed, showing significantly improved electromigration performance without degradation of signal transmission characteristics. Eye diagram measurements confirm negligible changes before and after reliability stress testing. In addition, the PCIe RDL interconnect structure is characterized by S-parameter measurements up to 100 GHz, validating its suitability for high-speed medium-reach links. By co-optimizing interconnect architecture, wiring pitch, and transmission distance, the proposed hierarchical RDL interposer architecture enables system-level reduction of interconnect energy consumption without sacrificing signal integrity or reliability. The architecture is technology-agnostic and can be applied to 2.5D RDL interposers, glass interposers, and glass-core substrates, providing a scalable and energy-efficient interconnect solution for future AI packages.

3:05 – 3:25
4.5 Inverse Hybrid Bonding for 3.5D Heterogeneous Integration on Glass Substrate
Wanshu Zeng, Madison Manley, Dipayan Pal, Ashita Victor, Andrew Kummel, Muhannad Bakir – Georgia Institute of Technology
This paper presents the first implementation of inverse hybrid bonding (IHB) on a glass-core 3.5D platform with a bonding gap of 1 µm and validates the process feasibility for substrates beyond silicon substrates. IHB enables flexible interconnects design, a batch scale underfill deposition, and reduced process complexity. Compared to conventional hybrid bonding, IHB is realized by forming the electrical interconnection prior to the deposition of the dielectric underfill. This work demonstrates IHB on a 3.5D test vehicle by integrating silicon dices with different interconnect pitches (10 µm, 100 µm, and 200 µm) onto a glass substrate using direct Cu-Cu thermal compression bonding with Au passivation, followed by vapor- phase atomic layer deposition of a metal–organic framework (MOF) underfill. Electrical and mechanical characterizations are conducted to verify the process reliability.

3:25 – 3:45 Afternoon Coffee Break

Session 5: Material & Process I
Chair: TBD

3:45 – 4:05
5.1 Contact and Interconnect Processes for Angstrom Scale Devices [Invited]
Robert Clark, TEL

4:05 – 4:25
5.2 Area Selective Deposition to Enable Sub-Lithographic End-To-End Patterning
Todd Ryan, Sudipto Naskar, Dominic Esan, Shrinath ghadge, Michael Majeski, John Richards, Michael Milgie, Martin McCallum, Paul Nyhus, Wallace Charles – Intel
Dielectric-on-dielectric (DoD) oxide deposition was used to pattern end-to-end (EtE) features in 25nm pitch interconnect lines fabricated using a self-aligned litho-etch-litho-etch (SALELE) patterning scheme. Oxide pillars were formed using the oxide DoD in a self-aligned block (SAB) pattern, which defined the EtE. After progressive improvement in the ASD deposition conditions, the ASD pillar process showed adequate selectivity to reliably form line end-to-ends. The process showed excellent defectivity results post-CMP. This study demonstrates that ASD SAB pillars are a viable option to enable sub-lithographic EtE patterning.

4:25 – 4:45
5.3 High-Aspect-Ratio Ruthenium Etch Optimization for Metal Pitch 18 Dual-Direct Metal Etch
Yiting Sun, Yanan Li, Vincent Renaud, Gilles Delie, Giulio Marti, Serena Rollo, Davide Tierno, Yannick Hermans, Evi Vrancken, Bart Kenens, Ivan Erofeev, Stefan Decoster, Chen Wu, Seongho Park – Imec
Ruthenium (Ru) patterning in Dual‑Direct Metal Etch flows is limited by plasma-induced oxidation of the silicon nitride hard mask, which causes bridging at high aspect ratios. We implement a segmented Ru etch-clean scheme and identify the key factors governing defectivity: the longest continuous etch, total etch time, rounds of cleaning, and the distribution of etching duration across segments. Bridging is suppressed by keeping each etch-segment below a cutoff time and placing the longest etch-segment at later stage, while line breaks are mitigated by limiting total etch time and minimizing cleaning rounds. These insights support more robust high-aspect-ratio Ru integration.

4:45 – 5:05
5.4 Improvement of Electrical Characteristics and Dielectric Relaxation of MIM Capacitor Using TiN Electrode Processing
Takeshi Ishizaki, Nobuyuki Ohba, Takamasa Yoshino, Hirosato Shintaku, Eiichiro Kanda, Yukihiro Shiraki, Takashi Kojima, Takaya Yamanaka, Yoshihisa Kagawa, Tomoyuki Hirano – Sony Semiconductor Solutions
We have successfully mass-produced a 3D-MIM capacitor with a trench structure that was fabricated in a conventional Cu interconnect layer. By improving the TiN electrode process, the electrical characteristics and dielectric relaxation were enhanced. Incorporating the 3D-MIM capacitor developed in this study as the pixel storage capacitor enables the production of image sensors with a high dynamic range

5:05 – 5:25
5.5 Remarkable improvement on plasma-induced damage via control of low-k deposition ramp rate during PECVD
Yongjun Ahn, Youngsoo Yoon, Huisu Yoon, Suil Lee, Wookhyun Lee, Hochul Lim, Hwasung Rhee – Samsung
In this paper, we reported facile method on reducing plasma induced damage (PID) in OMCTS deposition process. To control PID, the different heater distance was selected, and degree of PID was detected by LFRF available profile and test on gate leakage (Ig) TEG. As the heater distance decreased, degree of PID was reduced with decreasing charge density of electric field, however, this method has limitations in limiting the mass production margin and tool path. We found that the bulk OMCTS ramp rate had close relationship for PID. As the ramp rate decreased, the pore structure was closed and densified, resulting in efficient protection for excessive plasma charge. The decrease of the ramp rate showed improved gate oxide integrity and its quality regardless the heater distance.

WEDNESDAY, JUNE 3, 2026

8:15 – 8:55
Session 6: Keynote – Wiring the Future: From Contacts to Systems
Mukund Srinivasan – Applied Materials

Session 7: Reliability / Failure Analysis / Integration
Chair: TBD

8:55 – 9:15
7.1 Impact of Air-Gap Bottom Height on Line-to-Line Capacitance and Reliability of Fine-Pitch Tungsten Interconnects for 3D Flash Memory
Seiya Hirano, Yuuki Nagashima, Genki Sawada, Sota Araki, Mitsuhiko Noda, Masayoshi Tagami, Katsuyuki Sekine – Kioxia Corporation
This paper presents the development and characterization of subtractive-etched tungsten (W) bit lines incorporating engineered air-gap structures for 3D Flash memory interconnects. The results demonstrate that precise control of the air-gap bottom height suppresses electric-field fringing, resulting in a significant reduction in line-to-line capacitance and improved time-dependent dielectric breakdown (TDDB) reliability. The improvement in TDDB lifetime is also partly attributed to enhanced film quality of the inter-line dielectric formed on the surface of the W interconnects, which reduces the density of trap sites. These findings support the realization of high-speed, highly reliable 3D Flash memory.

9:15 – 9:35
7.2 Investigation of Highly-Reliabile Cu Interconnect with Upper W Vias for 3D Flash-Memory
Yohei Yamaguchi, Kanako Shiga, Hiroki Yamashita, Chikamasa, Chikamasa Yokoyama, Katsumi, Morii Morii, Shinya Arai, Koji Arita, Keita Yamamoto, Kensuke Ishikawa, Akihide Takahashi, Yasuo Kasagi – Kioxia Corporation
This work presents the highly-reliable copper (Cu) interconnect with high aspect ratio (HAR) upper tungsten (W) vias for 3D flash-memory. The high reliability of Cu interconnect is realized by controlling the film stress of upper HAR W via and interconnect, as well as Cu grain size. This process is useful for future 3D flash-memory which has sub-20 nm bit-line (BL) half pitch (HP) and HAR W via on BL.

9:35 – 9:55
7.3 Statistical analysis of in-wafer TDDB lifetime variability in Ru/Air-Gap interconnects
Kohei Nakayama, Nyamjargal Ochirkhuyag, Kazuyoshi Ueno, Shinji Yokogawa, Alicja Lesniewska, Gilles Delie, Olalla Varela Pedreira, Chen Wu, Kristof Croes, Seongho Park, Fumihiro Inoue – Yokohama National University
Variations in time-dependent dielectric breakdown (TDDB) within a 300 mm wafer were studied for direct metal etched ruthenium (Ru) / airgap (AG) interconnects with metal pitches (MPs) 20, 22, and 24 nm. The results show that the time to breakdown (tBD) increases with wider metal pitch and tends to be longer toward the wafer center. The in-wafer capacitance variation is consistent with the observed tBD variation trends, indicating that the variations in interconnect spacing dominate the tBD variability. Furthermore, for the MP20 nm, the lognormally distributed tBD observed over the entire wafer can be divided into concentric in-wafer regions that follow Weibull distributions, effectively removing the influence of spacing variation across the wafer. These results highlight the importance of accounting for in-wafer variability to achieve accurate TDDB lifetime prediction for Ru/AG interconnects.

9:55 – 10:15
7.4 Process-Induced Effects on TDDB Lifetime of MP18 DME Ru Interconnects
Alicja Lesniewska, Gilles Delie, Stefan Decoster, Koen Van Sever, Olalla Varela Pedreira, Chen Wu, Seongho Park – Imec
This work evaluates time-dependent dielectric breakdown (TDDB) at MP18 in direct metal etch Ru interconnect systems, focusing on integration improvements that deliver optimal TDDB performance. We systematically investigated the impact of specific process enhancements on reliability and identified the conditions required to achieve a 10-year lifetime target. Additionally, TDDB measurements were conducted at elevated temperatures and across both wafer-level and package-level configurations to assess the most effective testing methodology. Our results demonstrate that accurate lifetime extrapolation to lower voltages and percentiles requires testing at intermediate voltage ranges. These findings provide critical insights into reliability optimization for advanced interconnect technologies, supporting continued scaling for high-performance semiconductor devices.

10:15 – 10:35 Morning Coffee Break

Session 8: Advanced Interconnects II
Chair: TBD

10:35 – 11:00
8.1 Title TBD [Invited]
Jeff Leib, Intel

11:00 – 11:25
8.2 Advanced Novel Dielectrics for Sub-3nm Copper and Ruthenium Interconnect [Invited]
Son Nguyen, IBM Research

11:25 – 11:45
8.3 18-nm Pitch Subtractive Ru Interconnects:Process Development and RC Performance Validation
Jaemyung Choi, Sangbong Lee, Seungmo Ha, Youngtaek Oh, jisoo Lee, Yunho Kang, Jinwoo Kim, Gyuwan Choi, Minkyoung Lee, Kyung-Min Chung, Seunghye Baek, Myungho Kong, Seungjun Lee, Juhyun Kim, Sungjoo An, Taesun Kim, Donghoon Kwon, Jiho Song, Sukwon Lee, Kyoung-Woo Lee, Sang Wuk Park, Seung Hun Lee, Sangjin Hyun, Ilryong Kim – Samsung Electronics
As the BEOL metal pitch continues to scale down, achieving the desired metal resistance using conventional damascene Cu becomes increasingly infeasible. To address this challenge, significant research on a subtractive Ru scheme has been pursued. By implementing the subtractive Ru approach, not only does it offer the advantage of reduced metal resistance, but it also successfully lowers metal capacitance. In response to this need, this paper outlines the development strategy and results of the subtractive Ru scheme. By following this development pathway, we evaluated the RC characteristics of the resulting subtractive Ru interconnect and compared them with those of damascene Cu. The results confirm that the use of subtractive Ru leads to a 55 % reduction in line resistance and a 40 % reduction in line-to-line capacitance. Additionally, by improving specific process steps, the process maturity of subtractive Ru has been approached to a level comparable to damascene Cu at an 18nm pitch.

11:45 – 12:05
8.4 Integration of Ru Direct Metal Etch Interconnect with Cu Single Damascene: transition from Ru layer to Cu layer
Rollo, Serena; Marti, Giulio; Delie, Gilles; Sun, Yiting; Montero, Daniel; Kumar Mandal, Akhilesh; Varela Pedreira, Olalla; Wu, Chen; Park, Seongho – IMEC
In this paper we present two integration schemes combining Ruthenium (Ru) interconnects with Single Damascene Copper (Cu SD). The two schemes differ primarily in the formation of the inter metal via: the first employs a pillar type via realized through a Dual Direct Metal Etch (DDME) flow, while the second uses a Selective Metal Prefill Fully Self Aligned Via (Via Prefill FSAV) flow in combination with Ru direct metal etch (DME) at Mx level. We successfully integrated both approaches with Cu SD at Mx+1 level for the first time. The results were evaluated through post Cu metallization morphology and electrical characterization on Kelvin via (KV) structures. Thermal-storage tests were conducted to confirm the robustness of both schemes. Overall, the demonstrated Ru-Cu integrations not only support the transition beyond conventional Cu Dual-Damascene (DD) but also offer industry relevant pathways for manufacturable next generation back-end of line (BEOL) modules.

12:05 – 1:20 Lunch Break

Session 9: Material & Process II
Chair: TBD

1:20 – 1:45
9.1 ASD and ALE [Invited]
Mark Saly, Applied Materials

1:45 – 2:05
9.1 Patterning, Improved Epitaxial Quality, and Anisotropic E-test of Ion-Beam-Deposited In-Plane and Out-of-Plane Ruthenium Nanowires for Low-Resistivity Interconnects
Christopher Jezewski, Rutvik Mehta, Sai Siva Kumar Pinnepalli, Carly Rogan, Saima Siddiqui, Tristan Tronic, I-Cheng Tung, Ananya Dutta, Yuejing Wang, Deepti Jain, Ashish Kulkarni, Robert Caldwell, Michael Beumer, Travis Delashmutt, Noel Franco, Iulian Hetel, YuWen Huang, Robert Jordan, Emmannuel Khora, Brian Krist, Pratik Koirala, Adedapo Oni, Akshit Peer, Amish Shah, Matthew V. Metz, Mauro Kobrinsky – Intel Corporation
Ruthenium (Ru) is a leading candidate to replace copper (Cu) in advanced interconnects due to superior patterning fidelity among non-Cu metals, a critical advantage at scaled dimensions. The primary limitation of polycrystalline metals is high resistivity due to grain boundary scattering. This challenge has motivated the development of approaches to enhance crystallinity and control crystallographic orientation. This work evaluates whether epitaxial texture of Ru reduces line resistivity in subtractively patterned nanowires. Epitaxial [0001] Ru films with in-plane and out-of-plane orientations were grown under BEOL-compatible conditions using a Veeco IBD300TM dual-beam ion-beam deposition (IBD) process. We focus on line resistivity (R) measurements on in-plane epitaxial Ru. When patterned into nanowires with matched cross-sectional areas, in-plane epitaxial Ru demonstrated >22% lower line resistivity relative to conventionally sputtered polycrystalline Ru. Blanket resistivities approached bulk Ru for as-deposited out-of-plane films and annealed in-plane films. Cross‑sectional TEM confirms single-crystal character. Transport anisotropy within the measured angular range is at most weak and remains under investigation. These results indicate that epitaxial Ru with controlled crystallographic texture can reduce line resistivity at scaled dimensions under BEOL-compatible processing, supporting its potential for next-generation interconnect integration.

2:05 – 2:25
9.3 Ultra-low resistivity PtCoO2 Delafossite thin films via multilayer epitaxy for advanced interconnects
Jean-Philippe Soulie, Kerry Hazeldine, Silvia Armini, Johan Swerts, Chen Wu, Seongho Park, Zsolt Tokei, Christophe Adelmann – Imec
In this work, we demonstrate the deposition of epitaxial PtCoO2 thin films (<20-nm) on c-plane sapphire substrates using a multi-layer deposition strategy combined with high-temperature oxygen annealing. This approach significantly enhances crystallinity, reduces void formation, and minimizes surface roughness, yielding resistivities as low as 4.7µΩcm. Structural characterization demonstrates strong (001) orientation and excellent crystalline quality, while electrical benchmarking shows that optimized PtCoO2 films rival or surpass conventional interconnect stacks such as TaN/Cu/TaN and Ru. These findings establish PtCoO2 as a promising candidate for future interconnect metallization and underscore the critical role of interface engineering and oxygen control.

2:25 – 2:45
9.4 Textured PtCoO2 on Amorphous SiO2 Enabled by Ion Bombardment for BEOL Interconnects (Cancelled)
Taehoon Kim, Guanyu ZHOU, Yansong Li, Christian Lavoie, Vesna Stanic, Peter Kerns, Ching-tzu Chen, Christopher Hinkle – University of Notre Dame
Platinum cobalt oxide (PtCoO2) has recently attracted attention as a potential candidate for next-generation BEOL interconnects due to its high intrinsic electrical conductivity and thermal stability. While highly oriented PtCoO2 films grown on crystalline substrates exhibit low resistivity, integration into industrial BEOL processes requires growth on amorphous underlayers such as SiO2, where degraded crystallinity is commonly observed. In this work, we investigate ion-bombardment-assisted sputter growth of PtCoO2 thin films on amorphous SiO2 substrates as a pathway to enhance film crystallinity. Compared to films deposited without ion bombardment, ion-bombarded PtCoO2 films show significantly improved crystallographic texture, as confirmed by X-ray diffraction (XRD) 2&#952;-&#969; and Chi-scan analyses. These results demonstrate that ion bombardment can effectively promote crystalline ordering in sputtered PtCoO2 films on amorphous SiO2, providing a viable process knob for improving film quality on industry-relevant substrates. This approach establishes a structural foundation toward future optimization of PtCoO2-based oxide conductors for BEOL interconnect applications.

2:45 – 3:05
9.5 Plasma-induced damage control by atomic layer etching for low-resistance contact holes
Akiko Hirata, Masanaga Fukasawa, Hiroyuki Ota, Atsushi Yagishita, TETSUYA UEDA, Kenzou Manabe, Wataru Mizubayashi, Yoshihiro Hayashi, Meishoku Masahara – National Institute of Advanced Industrial Science and Technology
We investigated the improvement of contact resistance using atomic layer etching (ALE), which enables atomic-level process control. A comparison analysis of SiO2 ALE, SiO2 RIE, and SiN RIE for contact hole etching revealed that ALE significantly reduces contact resistance relative to that of RIE. The increase in contact resistance was primarily attributed to the SiOx layer formed under the Ti/TiN barrier metal, which was effectively suppressed by ALE. By separating the adsorption, desorption, and ashing processes, ALE allows independent optimization of each step, thereby reducing oxidation, and making it well-suited for precise control of contact resistance.

3:05 – 3:25 Afternoon Coffee Break

Session 10: DTCO & Modeling
Chair: TBD

3:25 – 3:50
10.1 AI Use in Materials Discovery [Invited]
Chris Hinkle, Notre Dame

3:50 – 4:10
10.2 IR-drop-based Electromigration-Compliance Checks of Grid Unit-Cells in Power Delivery Networks
Simone Esposto, Hosain Farr, Leslie Grate, Tony Chavez, Mischa Thesberg, Helena Schneider, Ivan Ciofi, Giuliano Sisto, Kristof Croes, Dragomir Milojevic, Houman Zahedmanesh – IMEC
This paper investigates the impact of redundancy on electromigration (EM) risk in unit cells derived from power delivery networks (PDN) in advanced technology nodes. Test structures were fabricated in a commercial 28-nm technology node with minimum feature sizes of 45 nm. For the first time, activation energy was extracted for PDN tiles composed of different metal dimensions, showing that it can vary depending on the adopted failure criterion and is related to the metallization layers present in the stack. Linewidth scaling worsens shunting effect, as void incubation in advanced nodes tends to produce near-open failures with a sharp resistance increase (~0.4 kΩ; for 45 nm lines). Nevertheless, the presence of redundant current paths can partially mitigate this effect by allowing current redistribution, delaying functional degradation. Further, in this study, a new chip-level reliability assessment methodology is proposed that considers available IR-drop margins rather than relying on the conventional resistance-change failure criterion, which is overly conservative and significantly impacts the reliability margin of PDN tiles. Finally, a three-dimensional TCAD simulator was calibrated with single line experiments and employed to validate experimental trends.

4:10 – 4:30
10.3 Relieving M1 Congestion in 10nm FD-SOI Standard Cells with a Low-Cost MOL Integration
Emmanuel Petitprez, Pierre Brianceau, Alexis Krakovinsky, Krunoslav Romanjek, Yves Maneglia, Olivier Billoint, Jorge Nacenta-Mendivil, Fabien Bringuier, Messaoud Bedjaoui, Valérie LAPRAS, Aussenac François, Ludovic Couture, Alexandre Magalhaes-Lucas, Gennie Garnier, Blandine Duriez, Marie-Claire Cyrille, Fenouillet-Beranger Claire – Université Grenoble Alpes, CEA, LETI
We present a low-cost MOL integration scheme tailored for advanced FD-SOI nodes, addressing interconnect congestion driven by increased standard cell density. Our approach introduces a thin SiCO layer beneath the contact etch stop layer, enabling contact extension beyond the active area without risking punch-through. Experimental validation demonstrates a significant enhancement in contact robustness through a punch-through-immune integration. At the design level, this innovation reduces M1 routing congestion and markedly improves logic cell routability, as evidenced by a 9-track AND-OR-INVERT standard cell case study implemented in 10nm FD-SOI technology.

4:30 – 4:50
10.4 Finite element analysis of airgap mechanical stability in Ruthenium nano-interconnects
Abdellah Salahouelhadj, Yao Yao, Kris Vanstreels, Gilles Delie, Giulio Marti, Oguzhan Orkut Okudur, Mario Gonzalez, Chen Wu, Seongho Park – imec
This study investigates the mechanical integrity of advanced ruthenium (Ru) back end of line (BEOL) interconnect structures incorporating airgaps using finite element modelling. Although airgaps are effective in reducing parasitic capacitance, they can also weaken the mechanical robustness of nanoscale interconnect and increase risk to reliability failures, particularly BEOL fracture. Delamination driven by chip-package interaction (CPI) loading is identified as a critical failure mode that requires detailed assessment. To address this, several Ru based BEOL architectures featuring different airgap implementations were modelled and evaluated. The corresponding energy release rates (G) at key material interfaces were computed and benchmarked against a non airgap reference structure. The results provide quantitative insight into the fracture susceptibility of Ru interconnects with airgaps and highlight the mechanical trade offs associated with different airgap placement strategies.

4:50 – 5:10
10.5 Atomistic Modeling of Twin Boundary Scattering in PtCoO2
Takahisa Tanaka – Keio University
Anisotropic conduction in delafossite materials, such as PtCoO2, efficiently suppresses the resistivity size effect induced by surface scattering. This paper reported atomistic modeling of grain boundary scattering, another primary origin of the resistivity size effect, in PtCoO2. To handle a large number of atoms, density functional tight binding (DFTB) parameters for PtCoO2 were developed using Bayesian optimization. The reflection coefficient of 180°-rotated twin boundary, a common grain boundary in delafossite, was evaluated from DFTB based non-equilibrium Green’s function scheme. The extracted reflection coefficient of 0.48 was in reasonable agreement with empirically used value of 0.5.

Poster Session and Conference Reception
Chair: TBD

5:30PM – 7:30PM, Wednesday June 3

P1. Integrating Single-Crystal Ruthenium in Advanced Interconnects by Layer Transfer
Christophe Adelmann, Jean-Philippe Soulie, Francois Chancerel, Steven brems, Anurag Vohra, Pawan Kumar, Benjamin Groven, Rajat Gujrati, Souvik Ghosh, Peter Kerepesi, Michael Dornetshumer, Florian Medl, Tobias Wernicke, Christoph Floetgen, Chen Wu, Seongho Park – Imec
Ru is a promising candidate to replace current Cu metallization due to its favorable resistivity scaling and potential for barrier-less integration. Single-crystalline Ru offers further advantages by suppressing grain-boundary scattering and mitigating line edge roughness due to anisotropic etching. This work introduced an integration scheme for epitaxial Ru interconnects, combining scalable epitaxial growth on AlN (0001)/Si (111) and MoS2-based templates with Ru-to-Ru wafer bonding, and solid-phase epitax-ial regrowth. Debonding strategies, including 2D-material-mediated release layers, enable transfer of high-quality Ru films onto device wafers. Together, these results outline a path toward low-resistivity, scalable interconnects for future technology nodes.

P2. Electrochemically Deposited Fine-Grain (fg-)Cu for Hybrid Bonding Applications
Chih-Hao Hsia, SungHo Park, Soichi Watanabe, Marco Arnold, Aleksandar Radisic, Herbert Struyf, Jo De Messemaeker, Zaid El-Mekki, Punith Kumar Mudigere Krishne Gowda, Sven Dewilde, Olivier Richard, Serena Iacovo – imec
We have successfully performed wafer-level (300 mm) fabrication of fine-grain copper (fg-Cu) features having wide range of characteristic dimensions (CD) and aspect ratios (AR). Physical-chemical properties of fg-Cu were examined, while possible challenges were explored in post-plating processing and integration of fg-Cu structures into existing hybrid-bonding production flows. Fg-Cu features were analyzed after various pre- and post-bonding process steps using Focused ion beam (FIB), Transmission electron microscopy (TEM), Atomic force microscopy (AFM), Precession electron diffraction (PED), and other techniques relevant for characterization of physical-chemical properties. The aim was to establish possible advantages fg-Cu could offer in hybrid bonding applications when compared to standard Cu, used in plating of damascene interconnects.

P3. Cobalt metallization processes for alternative applications on 300 mm wafer level
Conrad Guhl, Haosheng Wu, Tatiana Gurieva, Elena Schroetke, Felix Koehler, Robert Krause, marcus wislicenus, Benjamin Lilienthal-Uhlig – Fraunhofer IPMS-CNT
Cobalt metallization on 300 mm wafers for two non-traditional interconnect applications was investigated: (i) filling of high-aspect-ratio (500 nm × 14 µm) features, and (ii) formation of nanoscale micromagnets for spin-qubit devices. A pulsed Co-MOCVD process on ALD-TiN barriers yields conformal seed layers, enabling cobalt ECD with minimized voiding when operated at low current density. CMP of plated Co shows anneal-dependent removal rates from ~600 to 1100 nm/min, with good clearing and no detectable corrosion. For 40-150 nm micromagnet patterns, a TaN/Co barrier/seed stack plus Co-MOCVD/ECD enables void-free damascene fill, while CMP of isolated features exposes pattern-dependent clearing non-uniformities that require layout-specific and anneal-assisted process optimization.

P4. Improved Crystallographic Alignment and Grain Size of Metals on MoS2 for Sub-10-nm Interconnects [Student Paper]
Xunqiandi Cao, Ran Li, Fevronia Andreou, Zhenping Wang, Reza Motallebi, Enzi Zhai, Farhan Zahin, Cong Su, Kelvin Y. Xie, Yuxuan Cosmi Lin – Texas A&M University
Continued scaling of back end of line (BEOL) interconnects pushes metal line widths toward the electron mean free path, where surface and grain-boundary scattering significantly increase resistivity in polycrystalline metal films. Here, we propose that 2D materials such as monolayer MoS2 can work as a van der Waals template for metal growth at room temperature. Transmission electron microscope (TEM) studies indicate that Cu, Ru, and Au films grown on MoS2 can achieve larger grain sizes and improved in-plane crystallographic alignment compared with metal films deposited on amorphous carbon TEM grids. These improvements are attributed to interfacial energy minimization enabled by Moiré-superlattice-mediated alignment, which reduces lattice mismatch and promotes low-angle grain boundaries and grain coalescence.

P5. Selective Thermal Chemical Vapor Deposition of SiAlOx on SiCOH in Preference to Cu for Etch Resistivity Enhancement on the NanoScale
Xinyu Wang, Jing Mu, T. Wong Keith, Srinivas Nemani, Ellie Yieh, Ajay Yadav, James Huang, Andrew Kummel – UC San Diego
Selective dielectric-on-dielectric (DOD) deposition of ~1 nm SiAlOx was demonstrated on Cu/SiCOH patterned substrates using vapor-phase aniline passivation combined with a dual-temperature, water-free pulsed CVD process. Aniline selectively inhibited nucleation on Cu, while an AlOx/SiOx supercycle enabled controlled growth on SiCOH. In situ XPS confirmed formation of over 1 nm SiAlOx on dielectric regions with no detectable Al or Si incorporation on Cu. Cross-sectional TEM and EELS verified nanoscale selectivity, showing a conformal SiAlOx deposition exclusively on SiCOH. On patterned samples, this selectively deposited film reduced dielectric recess during CHF3/Ar reactive ion etching from 11 nm to 5 nm, demonstrating improved dielectric etch resistance in Cu/SiCOH interconnect structures.

P6. Enhancing Oxide/Nitride Selectivity in Area-Selective Atomic Layer Deposition via Pyridine-Catalyzed Inhibition
Jieun Oh, Woohyuk Kim, Woo-Hee Kim – Hanyang University
Area-selective atomic layer deposition (AS-ALD) is a key bottom-up approach for self-aligned nanofabrication in advanced semiconductor devices. In this work, we present a pyridine-assisted inhibition strategy that enhances the adsorption of volatile small molecule inhibitors (SMIs) on non-growth areas (NGAs) without altering the intrinsic surface chemistry. Trimethylsilyl chloride (TMS-Cl) and (N,N-diethylamino) trimethylsilane (DEATMS) were employed as representative SMIs to selectively suppress Ru ALD on -NH terminated SiN and -OH terminated SiO2 surfaces, respectively. Vapor-phase pyridine pretreatment effectively delayed nucleation and suppressed Ru growth, leading to enhanced selectivity between growth and non-growth surfaces. This catalyst-assisted approach offers a simple and scalable strategy for substrate-selective inhibition in AS-ALD.

P7. Interface Engineered ALD MoxP1-x Thin Films and Their Transport Properties
Ayaka Sasaki, Jeremie Dalton, Jeong-Seok Na, Kenshin Inagaki, Masamitsu Tanaka, Kensei Kugio, Munehiro Tada – Keio University
Molybdenum phosphide (MoP), categorized as a topological semimetal, exhibits promising electronic transport characteristics, making it a strong candidate for low-resistivity interconnects. In this work, Mo-rich, MoxP1-x thin films are fabricated via atomic layer deposition (ALD). The film composition is tuned by alternating Mo and MoP deposition cycles to achieve Mo/MoP laminate thin films. By optimizing the laminated deposition sequence to control interface density, both the room-temperature and low-temperature resistivity are significantly reduced. The more finely layered laminate exhibits suppressed electron boundary scattering, characterized by a reflection coefficient (R) of 0.07 in the Fuchs-Sondheimer and Mayadas-Shatzkes (FS–MS) model, significantly lower than that of copper (Cu) thin films. Low temperature measurements further show that Residual Resistivity Ratio (RRR) is independent of the film thickness, indicating a minimal size effect on resistivity. These results demonstrate that Mo-rich, MoxP1-x films are highly promising interconnect materials for both room temperature and cryogenic applications.

P8. CMOS-compatible Method of Scaling Nanowire Bump Fabrication for Heterogeneous Integration
Danish Ahmed Baig, Muhannad Bakir – Georgia Institute of Technology
Scaling of bonding tiers in advanced packages has been enabled by thermocompression and hybrid bonding, which require significant process cleanliness and tight tolerances. Compliant interconnects, such as nanowire bumps, provide a potential low-temperature alternative. This work demonstrates a novel CMOS-compatible process flow for scaling nanowire bump pitch using an aluminum contact rail and a one-step, low-contamination release process for template-assisted growth. A 64 percent reduction in pitch (20 microns) is demonstrated for this interconnect class.

P9. CoSn Pseudo-one-dimensional Conductor: Potential and Chellenges for Interconnect Applications
Tomoya Nakatani, Rohit Dahule, Nattamon Suwannaharn, Taisuke Sasaki, Ryoji Sahara – National Institute for Materials Science
As a candidate of an interconnect material that overcomes the resistivity scaling limit of Cu, we investigated CoSn kagome metal with a pseudo-one-dimensional electronic transport property. Single-crystalline CoSn(10-10) thin films were grown on MgO(110) with Ru buffers, exhibiting strong resistivity anisotropy (~13 and 120 micro Ohm cm depending on crystallographic orientation). While the CoSn(10-10) exhibits three-dimensional island-like growth which causes surface roughness in thin films, CoSn shows significant potential for future nanoscale interconnects.

P10. Neural-Network-Potential Molecular Dynamics Study of Nb Plasma-Enhanced ALD for ULSI Interconnects
Yukihiro Shimogaki, Jun Yamaguchi, Noboru Sato, Akimasa Nakashima, Tomoko Hirabaru, Masao Arashida, Naoki Tamaoki, Atsuhiro Tsukune – The University of Tokyo
Niobium (Nb) is a promising candidate for advanced interconnects and is also of interest for cryogenic CMOS due to its superconducting properties. We develop a low-temperature (100-250 °C) plasma-enhanced ALD (PEALD) process for Nb using NbCl5 and employ neural-network-potential molecular dynamics (NNP-MD) to elucidate impurity formation/removal mechanisms under plasma and substrate bias. The simulations identify excessive NbCl5 adsorption as the origin of chain-like NbCl4 species that lead to residual Cl incorporation, and further reveal a process window where moderate Ar+ bombardment removes NbCl4 without damaging the surface, whereas overly strong bias promotes hydrogen ion penetration with limited reduction benefit. Guided by these insights, we optimized the bias sequence and reduced the chlorine concentration from 1.98 at.% to 0.33 at.%.

P11. Low Resistive Ni thin film with ultra-thin Al capping layer for Advanced Interconnects
Kensei Kugio, Ayaka Sasaki, Yusuke Mizobata, Kaito Tabata, Rozu Henmi, Sho Hamano, Takahisa Tanaka, Munehiro Tada – Keio University
Ni thin films covered with a 1nm Al thin capping layer achieves a low resistivity of µΩ·cm at a thickness of 7.9 nm, satisfying the 400C thermal budget requirement. XRR measurement reveals that the Al capping layer partially transforms into a passive Al2O3 layer, effectively suppressing the oxidation of the underlying Ni during annealing. XRD analysis indicates that annealing promotes Ni grain growth from 7 nm to 11 nm, directly contributing to the reduced resistivity. In contrast, Ni films without Al capping or NiAl intermetallic compounds exhibit higher resistivity under the same thermal conditions. Al-capped Ni serves as a promising candidate for ultra-thin interconnects below 10 nm thick, proving that oxidation control and suppression of the size effect are essential for maintaining low resistivity as Ni-based interconnects continue to scale down.

P12. Air-stable Low Dielectric Constant SiOx/AlOx Nanolaminate Films Deposited By Isothermal Pulsed Chemical Vapor Deposition With Carbon Doping And Forming Gas Annealing For Interlayer Dielectric
Jing Mu, Xinyu Wang, Kesong Wang, Jit Dutta, Dipayan Pal, Michael Breeden, T. Wong Keith, Srinivas Nemani, Ellie Yieh, Andrew Kummel – UC San Diego
A low-k, low-leakage, air-stable inorganic SiOx/AlOx film with N,N-dimethyltrimethylsilylamine (DMATMS) incorporation was successfully fabricated using an isothermal CVD process. This performance is achieved by dosing DMATMS during the purge section between the aluminum-tri-sec-butoxide (ATSB) and tris(tert-butoxy) silanol (TBS), combined with 400 °C forming gas annealing (FGA), enabling precise control over the film’s composition and structure. In addition to its low dielectric constant(k<3), the film demonstrates very low leakage current (10-8 A/cm2) at 1MV/cm after the 400 °C FGA, making it suitable for some back-end-of-line (BOEL) applications. Fourier-transform infrared spectroscopy (FTIR) results validate the influence of DMATMS doping and 400 °C forming gas annealing (FGA) on the film structure. X-ray reflectivity (XRR) analysis confirms the low density and porous structure of the film. This study demonstrates an isothermal deposition process with carbon doping and 400 °C FGA for producing an air-stable, inorganic film with low k and low leakage current.

P13. Enhancing CMOS Image Sensor Yield with TSV Liner Etch Optimization Using Virtual Fabrication
Pengfei Lyu, Qingpeng Wang, Caigan Chen, Lifei Sun, Ruxun Yuan – Lam Research Corporation
CMOS Image Sensors (CIS) have developed quickly in recent years. One particularly challenging in CIS process involves the TSV liner etch process needed to create Backside Illumination (BSI). In this paper, we model the BSI via liner etch process using virtual DOE to determine the optimal process window. ME time and OE time in each cycle, along with the number of cycle times, are the most important parameters in the via liner etch process. Over one hundred virtual DOE are performed to determine an optimal process window. The virtual DOEs in this study can accelerate new process development and process window optimization compared with Si experiment.

P14. N2 Plasma Passivation of In-Situ Vapor Cleaned Cu for Advanced Packaging
Hyeokin Ko, Jit Dutta, Andrew Kummel – UC San Diego
Hybrid bonding represents the most advanced interconnect technology for back-end copper interconnects. This process involves bonding of two wafers or chiplets through insulator-to-insulator contact, followed by heat treatment to promote copper interdiffusion and establish continuous Cu connection. Carbon containing additives in CMP aqueous solution as well as post wet clean air exposure leads to the formation of oxy-carbides. The contamination must be removed and, given the necessary queue time in interconnect fabrication, surface protection is critical. This study employs cyclic oxidation-reduction as the post-CMP cleaning method and introduces an in-situ N2 plasma process to form Cu4N on the surface, serving as a diffusion barrier against oxygen and carbon contamination. The in-situ X-ray Photoelectron Spectrometer (XPS) is employed to investigate the Cu 2p binding energy shift towards the higher energy (932.2 eV to 932.9 eV), which is evidence of the formation of Cu4N on the surface along with the N1s peak signal. The controlled decomposition of Cu4N at the interface is essential to complete the bonding process, as residual Cu4N can increase interfacial resistance.

P15. Impact of Forming Gas Annealing on the Structural and Electrical Properties of PtCoO2
Kerry Hazeldine, Jean-Philippe Soulie, Liam Dwyer, Alex S Walton, Chen Wu, Seongho Park, Christophe Adelmann, Silvia Armini – imec
PtCoO2 is a promising delafossite oxide for next generation interconnects due to its intrinsically low resistivity; but its behavior under back-end-of-line (BEOL) relevant conditions remains poorly understood. In this study, PtCoO2 thin films of varying thicknesses underwent forming gas annealing (FGA), and their structural, chemical, and electrical stability were evaluated. The FGA induces a partial reduction of Pt and Co, accompanied by the formation of a CoPt alloy and a loss of PtCoO2 crystallinity. These changes lead to degraded surface morphology and a significant increase in sheet resistance, reaching up to a ten fold increase in ultrathin films. The results demonstrate the strong sensitivity of PtCoO2 to hydrogen containing environments and highlight key challenges for its integration.

P16. Thickness Dependent Thermal Boundary Conductance in Utrathin BEOL-Compatible ALA h-BN films
Diego Contreras Mora, Ping Che Lee, Amy Ross, Haripin Chandra, Larry Chen, Ravi Kanjolia and Mansour Moinpour,  Andrew Kummel – University of California San Diego
Hexagonal boron nitride (h-BN) is an attractive BEOL dielectric due to its low permittivity and high in-plane thermal conductivity; however, low temperature depositions typically yield disordered films that impede cross-plane heat extraction. As interconnect dimensions scale below 60 nm, thermal resistance becomes interface-dominated, rendering diffusive heat transport inadequate. Here, we demonstrate a BEOL compatible (350 °C) atomic layer annealing (ALA) process that produces vertically aligned, crystalline h-BN thin films exhibiting cross-plane ballistic phonon transport at interconnect relevant thicknesses. Steady-state thermoreflectance measurements reveal effective cross-plane conductance in the range of 130 – 160 MW m-2 K-1 and weak thickness dependence below 60 nm, consistent with ballistic transport dominated by interfacial resistance. In-situ XPS confirms low carbon and oxygen incorporation during growth. These results establish vertically aligned h-BN as a BEOL compatible dielectric capable of enabling ballistic cross-plane heat transport at nanoscale thicknesses, offering a practical route to mitigate interface dominated thermal bottlenecks in advanced interconnect architectures.

P17. Phase Formation and Stabilization of Delafossite PtCoO2 Thin Films Grown by Atomic Layer Deposition
Joonho Moon, Sung Min Jung, Gayun Kim, Seung-heon Chris Baek, Hyung-jun Kim, Chanyoung Yoo, Kiyoung Lee – Hongik University
Delafossite PtCoO2 thin films were deposited by atomic layer deposition (ALD) and crystallized via post-deposition annealing (PDA). The composition and phase stability of the delafossite PtCoO2 was engineered by adjusting the ALD cycle ratio of Pt and Co3O4. The crystallinity and thickness-dependent electrical transport of PtCoO2 thin films were investigated as a function of annealing temperature. X-ray diffraction indicates that PDA at 650 oC results in incomplete delafossite formation with residual CoO2 phase, while 800 oC induces a Pt-rich secondary phase. In contrast, PDA at 700 oC shows phase-pure delafossite PtCoO2 with a preferred out-of-plane orientation. Notably, an 8.7 nm PtCoO2 film annealed at 700 oC on SiO2 exhibits the lowest resistivity of 25.7 µΩ·cm with a reduced thickness-dependent resistivity increase. These results highlight that precise PDA control is critical for stabilizing the delafossite PtCoO2 and achieving favorable electrical transport properties in ALD-grown films for interconnect applications.

P18. Nano-scale Assessment of the Copper Cyclic Cleaning in Hybrid Bond Interconnects
Jit Dutta, Hyeokin Ko, Andrew Kummel – UC San Diego
Hybrid bonding has emerged as a leading integration strategy for advanced back-end copper interconnect architectures. However, carbon-based additives in CMP slurries, combined with post-clean air exposure, promote the formation of surface oxy-carbide species that degrade copper surface quality. Given the required queue time in interconnect manufacturing, effective contamination removal and subsequent surface protection are essential. This study proposes a dry cyclic cleaning methodology to restore copper surface integrity. The cleaning strategy comprises two sequential oxidation–reduction sub-cycles designed to eliminate surface contaminants selectively. AFM measurements indicate a more than three-to-fourfold improvement in surface roughness after treatment. SEM-EBSD analysis shows that crystallographic indexing increases from below 1% to above 90%, while cross-sectional TEM confirms a reduction in the thickness of the contaminated layer from ~30 nm to ~6 nm.

P19. Complete first-principles screening of MAX-phase materials for back-end-of-the-line interconnects
Lily Joyce, Michael Haverty, Joung Joo Lee, Bencherki Mebarki, Ravishankar Sundararaman – Rensselaer Polytechnic Institute
The resistance of nanoscale interconnects is greatly increased due to electron scattering at the surfaces of the interconnect and at grain boundaries. Directional conductors with minimal Fermi velocity towards the interconnect walls can minimize surface scattering and potentially outperform conventional interconnect metals such as copper. Here, we use first-principles calculations to computationally screen all 1,080 possible MAX phases, a class of materials that are promising for low resistivity in thin films. We characterize their suitability to replace copper in interconnects based on stability, bulk resistivity and nanoscale resistivity increase. We identify the five most promising MAX phases and predict their resistivity with varying film thickness and wire dimensions to contrast with copper.

P20. Breaking the Thickness-Continuity Limit: Ultrathin ALD Pt via Novel Chemical Continuity Enhancement
Jay Chiu, Isiah Liu, Sergei Ivanov, Randall Higuchi, Chang-Won Lee, Bhushan Zope – EMD Electronics
Scaling interconnects to the 2 nm node requires overcoming the resistivity bottleneck of ultrathin films. This work establishes an atomic layer deposition (ALD) process for Platinum (Pt) using a novel Pt-EM01 precursor and ozone O3. We identified a robust growth window at $150 – 250℃ but unveiled a critical trade-off: while O3 minimizes nucleation delay, excessive dosage degrades continuity via agglomeration. To surmount Volmer-Weber island growth limits, we introduce a post-deposition Chemical Continuity Enhancer (CCE). This treatment triggers surface diffusion, redistributing Pt mass from isolated islands into quasi-2D layers. Quantitative HAADF-STEM analysis confirms significant planarization, reducing the roughness coefficient of variation (CV) from 0.052 to 0.020. Consequently, the resistivity of sub-5 nm films drops from 3100 µΩcm to 38.5 µΩcm, achieving PVD-level conductivity.

P21. Morphological Transition-Driven Phase Separation in CoxTi1-x Ultra-Thin Film: Thickness-Dependent Kinetic Scaling
Gayun Kim, Joonho Moon, Yun Hee An, Hwanhui Yun, Young Geun Joo, Kiyoung Lee – Hongik University
This study characterizes the thickness-dependent morphological transition in CoxTi1-x thin films and its anomalous resistivity size effect. The resistivity exhibits a minimum value at a critical thickness (dcrit), marking the threshold between 2D-like planar growth and the onset of 3D columnar morphology. Kinetic analysis using an Arrhenius relationship yields an effective activation energy (Ea) of 0.34 eV, confirming that low-energy grain boundary diffusion governs the redistribution of alloying elements. While the 2D regime facilitates efficient phase separation, the transition to 3D growth introduces vertical grain boundaries that act as kinetic traps for metallic elements, driving the observed resistivity increase. These results establish a predictive framework for identifying the onset of 3D growth in alloy-based systems, providing fundamental design rules for advanced semiconductor metallization.

P22. Electrical–Thermal Co-Design and Fabrication of an Interlayer Copper Bridge for 3D mmWave Systems [Student Paper]
Wanshu Zeng, Young Jin Lee, Muhannad Bakir – Georgia Institute of Technology
This work presents a multifunctional interlayer Cu bridge for electrical interconnections and thermal management in 3D heterogeneously integrated millimeter-wave (mmWave) systems. The proposed architecture utilizes a Cu bridge with openings that encapsulates the chip, providing simultaneous cooling and grounding, while Cu pillars located within the patterned openings enable low-loss signal interconnections. Preliminary simulation results demonstrate that the architecture exhibits an insertion loss of less than 0.5 dB at 170 GHz, while maintaining the junction temperature below 85 °C for a chip dissipating 100 W/cm². Both the vertical signal paths and thermal structures are fabricated in a single electroplating step and enable simultaneous Cu-Cu direct bonding.

P23 Analysis of Material Processing in RuAl Interconnects
Nyamjargal Ochirkhuyag, Kohei Nakayama, Taisuke Sasaki, Kazuyoshi Ueno, Toyohiro Chikyow, Tadakatsu Ohkubo, Fumihiro Inoue – Yokohama National University
New materials beyond copper (Cu) in interconnects are on demand to keep lower resistivity in nanoscale and prevent metal-diffusion to dielectric layer. Both pure metal such as ruthenium (Ru) and binary metals is promising, particularly the ruthenium-aluminide (RuAl) exhibits high thermal stability, good electromigration reliability than pure Ru. This study investigates the low resistivity characteristics and chemical mechanical polishing (CMP) behavior of RuAl, which shows a higher material removal rate than Ru under both unannealed and annealed conditions.

P24. Integration learning to enable Mo as the next generation metal for contacts
Na Zhang, Paul Besser, Ben Natinsky, Kyle Blakeney, Chris Anthony Lingao, Brian Reiss, Kevin Dockery – Entegris
We investigated the influence of Molybdenum (Mo) deposition chemistry, stack architecture and microstructure on subsequent chemical mechanical polishing (CMP) performance, a critical module for enabling Mo integration. Mo films were deposited using multiple chemical precursors, PVD conditions and process sequences. These film stacks were selected to simulate fill and overburden in features and to generate a broad diversity in crystal structure and grain size. CMP performance was evaluated using a Mo-optimized slurry formulated to deliver high removal rates with minimal corrosion. The observed Mo removal rates (RR) of Mo stacks in this study were similar, despite different deposition methods and film crystal structures. The formulated slurry chemistry neutralized the differences in microstructure in the Mo films, suggesting deposition can be optimized for feature fill (enabling broad flexibility), knowing the CMP process is robust.

P25. Incidence-Angle-Dependent Specularity of Surface Scattering: Impact on Spatially Resolved Conductivity and Via Resistance
Redwanul Mahbub Talukder, Sumeet Gupta – Purdue University
Process-induced surface roughness on the interconnect sidewall leads to specular surface scattering, which has a significant effect on the line metal and via resistances. While several conductivity models utilize specularity (p) as a constant parameter, it has been shown that, in fact, (p) is a function of the incidence angle of electrons on the surface (θ). In this paper, we consider the no-correlation limit of surface roughness and study the impact of θ -dependent p on the spatial profile of conductivity across the metal cross-section and via resistance (accounting for both surface scattering and grain boundary scattering). For this, we incorporate p(θ) in the spatially resolved conductivity models and include these models in a 3D COMSOL-based simulation framework for vias. We compare the results for θ-dependent p with constant p showing a significant difference in the spatial distribution of conductivity under certain conditions, resulting in a considerable deviation in the predicted via resistance. The resistance difference reaches up to ~22% in aggressively scaled vias (e.g. lower level vias in the 7nm technology node) but decreases for larger geometries.

P26. Inherent Area-Selective Deposition of Ru Using an H2 Process for Advanced Interconnect Applications
Yohei Uchiyama, Yohei Kotsugi, Tomohiro Tsugawa, Ryosuke Harada – TANAKA PRECIOUS METALS TECHNOLOGIES Co., Ltd.
The next-generation interconnects such as sub-10 nm technologies are becoming finer and more complex. Therefore, it is anticipated that not only a reconsideration of the materials used to date but also a shift to entirely different processing approaches will be required. As a promising candidate, ruthenium (Ru) has attracted significant attention for metal lines material owing to its short electron mean free path and high electromigration resistance. Regarding the processes required to achieve fine-pitch structures, area-selective deposition (ASD) techniques are advancing. In this study, we report a simple ASD approach that exploits the intrinsic difference in nucleation delay of Ru precursors at relatively low deposition temperature. A Ru precursor [Ru(TMM)(CO)3] used in this study showed a difference in nucleation delay between the metal surface and the oxide and nitride surfaces. Based on the difference in Ru film thickness grown on them, the substrate selectivity index S was defined and confirmed to indicate positive selectivity (S > 0). Deposition experiments demonstrate that ~16.9nm of Ru can be selectively grown on Cu without any gas switching or inhibitor steps, while growth on TiN, SiO2 and low-k is suppressed to 0 nm. This inherently selective, single-process approach provides a practical pathway for Ru bottom-up interconnect fabrication and advanced metallization integration.

P27. Localized Electochemical Manufacturing for Fine-Line RDL Metallization
Robin Davis – Syenta
The rapid growth of artificial intelligence (AI) and high-performance computing (HPC) systems has driven increasing demands on package-level interconnect density, bandwidth, and power efficiency. In advanced packaging architectures employing chiplets and high-bandwidth memory (HBM), the redistribution layer (RDL) has emerged as a critical scaling bottleneck, with significant implications for manufacturability and cost in outsourced semiconductor assembly and test (OSAT) environments. Conventional semi-additive and modified semi-additive copper processes (SAP and mSAP) face increasing challenges as feature sizes approach sub-2 µm line/space geometries, resulting in narrowing process windows and non-linear cost escalation as routing density and layer count increases. This work presents a localized electrochemical manufacturing (LEM) approach for copper RDL fabrication that restructures electroplating by transferring pattern definition and current delivery from the wafer or panel surface to a patterned local electrode. By decoupling copper growth from lateral current transport through the seed layer, LEM mitigates key constraints that limit semi-additive scaling. Representative SEM images demonstrate uniform 1.1µm line/space copper features fabricated using the LEM process. A qualitative comparison with conventional RDL metallization approaches highlights implications for scalability, process margin, and cost behavior in advanced AI and HPC applications.

P28. Accelerating Low-Resistivity Metal Precursor Development for AI Devices Through Molecular Modeling and Simulation
Tse-An Yeh, Josh Yeh, Albert Chen, Paul Besser – Entegris
A low temperature, O-free, thermal ALD Ru process was revealed substrate-dependent selectivity (TiN, SiN, and SiO2 substrates). In order to understand the substrate-dependent adsorption and desorption mechanisms, Density Functional Theory (DFT) and Molecular Simulations were leveraged, revealing that hydrogenation of the precursors unsaturated carbon ring promotes ligand release and exposes reactive sites for nucleation. The calculated reactivity trend (TiN > SiN > SiO) aligned with experimental data, validating DFT’s predictive capability and accelerating precursor screening.

P29. Enabling Thick Copper CMP Applications Through Innovative CMP Slurry Design
Dnyanesh Tamboli, Pritpal Singh Dhillon, Juan Jiang, Stan Tsai, zhou hongjun – EMD Electronics
Copper CMP for thick films is transitioning from a specialized process to a key enabler for next-generation integration. The push toward copper-filled, high-aspect-ratio features deeper than 1 µm, driven by heterogeneous 3D assembly, advanced packaging, and backside power architectures demands fast and controllable planarization. At the same time, rising volumes of analog and mixed-signal products, which frequently incorporate larger and deeper copper geometries, intensify the need for high-productivity CMP solutions. Thick-overburden polishing places stringent requirements on slurry design: sustained high removal rates with corrosion suppression, strong step-height reduction to limit plated overburden, excellent within-wafer rate control over extended polish times, and effective copper ion management to preserve pad condition and minimize defects. We describe a slurry development strategy tailored to these constraints and enable thick copper CMP applications with high throughput, low defectivity and low cost of ownership.

P30. Copper Reduction and Silicon Dioxide Hydroxylation by Vacuum Ultraviolet Light Irradiation for Hybrid Bonding
Takeyasu SAITO, Hosei AKAMATSU, Kaito KATAYAMA, ENDO Shinichi, Naoki OKAMOTO – Osaka Metropolitan University
We aim to clean and reduce a copper oxide surface through Vacuum Ultraviolet (VUV) light irradiation in a 3% hydrogen atmosphere. It was found that contact angle decreases and Cu/Cu2O peak area ratio to CuO increases, showing surface wettability improvement and reduction of copper oxides. We also investigated silicon dioxide hydroxylation through VUV light under various atmosphere to evaluate Si-OH amount quantitatively by chemical modification XPS method.

P31. Dielectric Constant and Etch Resistance of Al2O3 and HfO2 HK Etch Stop Layers for Advanced Low K Interconnects
Jimmy Huang, Yi-Xian Chen, Tse-An Yeh, Albert Chen, Paul Besser – Entegris
Etch Stop Layers (ESL) serve a critical role in advanced interconnect structures, reducing line-to-line leakage and enabling dimensional scaling. As device scaling pushes dielectric stacks toward more complex material combinations, the atomic interaction between low-k and high-k components of the ESL is becoming an important factor in determining overall electrical performance. Density functional theory (DFT) calculations were performed to calculate the dielectric constant of stacked structures composed of low-k SiOC and two high-k metal oxides, Al2O3 and HfO2. Results show that integrating SiOC with Al2O3 slightly reduces the overall dielectric constant, whereas combining SiOC with HfO2 leads to a significant increase. Overall, our results suggest that material selection on the high-k material plays an important role in determining the dielectric response of the stack dielectric. Using a machine-learning force field to perform reactive-ion-etching molecular dynamics, we find that both Al2O3 and HfO2 develop fluorinated amorphous layers of ~13Å and ~20Å, respectively. Species-resolved trajectories show that Al2O3 primarily emits AlF3 through both sputtering and volatilization, whereas HfO2 predominantly releases HfF4; via post-collision volatilization. Under steady-state conditions, Al2O3 exhibits an etching rate approximately 2.2× that of HfO2.

P32. Electromigration Behavior of Hybrid Bonded Cu Microbumps: Effect of Dielectric, Metal, and Interface Properties [Student Paper]
Christopher Morrissey, Shubhra Bansal – Purdue University
This study adopts a comprehensive modeling approach to evaluate the effect of dielectric metal interconnect properties on the electromigration lifetime of hybrid bonded copper microbumps. The dielectrics investigated were SiO2/SiCN and two types of polyimides with varying modulus and coefficient of thermal expansion (CTE). SiO2/SiCN whose CTE was less than copper induced a compressive hydrostatic stress in the interconnect while the two polyimides whose CTEs were higher than copper induced a tensile stress. Increasing the CTE also seemed to change the distribution of the different elements of the vacancy flux vector norm while leaving the total flux magnitude unchanged. With regards to void surface velocity, the organic dielectrics had a higher velocity relative to SiO2/SiCN with the pores elongating along the direction of the current. The effective charge number changed the distribution of the different elements of the flux vector norm as well as the difference between the maximum and minimum vacancy concentrations. The energy of vacancy formation changed the magnitude of the vacancy flux vector norm while not changing the relative contribution of the different elements. Further studies on the effect of diffusion coefficient and metal microstructure are currently underway and will be discussed in the presentation.

P33. An Opportunity for Stacked Segmented TSV Architecture Based on 40:1 Aspect Ratio Etched Vias [Student Paper]
Geyu Yan, Muhannad Bakir – Georgia Institute of Technology
Scaling through-silicon vias (TSVs) toward higher density in heterogeneous integration (HI) is increasingly constrained by aspect-ratio (AR) limits in TSV fabrication. This work introduces a segmented TSV architecture that decouples TSV density from TSV length by vertically stacking multiple high-AR TSV tiers. Vias in the unit tier are etched using an optimized Bosch process, enabling formation of 40:1 AR vias with a diameter of 2.23 µm. Under a 40:1 AR fabrication limit, increasing the monolithic TSV length from 150 µm to 450 µm results in a 9× reduction in TSV density. In contrast, the segmented architecture preserves a constant high TSV density (~17,800 counts/mm2) independent of effective TSV length. The proposed approach provides a potential pathway for realizing very deep, high-density TSV interconnects and is compatible with hybrid bonding and TSV-integrated microfluidic cooling.

P34. Mitigation of Leakage in Hafnium Oxide Caused by TiN ALD Using Forming Gas Anneal
Amy Ross, Xinyu Wang, Shreyam Natani, Diego Contreras Mora, Adrian Alvarez, Walter Hernandez, Andrew Kummel – University of California San Diego
Hafnium oxide (HfO2) is a critical high-k dielectric in advanced microelectronic stacks, where ultrathin titanium nitride (TiN) diffusion barriers are commonly deposited by atomic layer deposition (ALD). However, TiN ALD precursors can introduce impurities into adjacent HfO2 and other gate oxides, creating electrically active defects that increase leakage current. In the present study, precursor-specific effects are isolated using controlled half-cycle exposures of TiCl4, NH3, and N2H4 on 4 nm HfO2, and compared against devices incorporating a 2 nm ALD TiN layer using TiCl4 + NH3 or TiCl4 + N2H4. Prior to FGA annealing, NH3 and N2H4 exposures increased leakage to ~1 A/cm2 at -5 MV/cm relative to ~10-4 A/cm2 for TiCl4 exposure and ~10-5 A/cm2 controls. FGA suppressed leakage by multiple orders of magnitude, restoring most devices to near-control leakage (~10-9 A/cm2) at -5 MV/cm. TiCl4-exposed and TiN-capped devices retained higher post-FGA leakage, suggesting chlorine-related defects limit the achievable leakage floor. ALD TiN/HfO2 made with TiCl4 + N2H4 had the same leakage as films made with TiCl4 + NH3 before FGA (1 A/cm2) and after FGA (10-8 A/cm2). This indicates that hydrazine is viable as a replacement for the industry standard of ammonia.

P35. Advanced BEOL Process Integration and Characterization of Selectively Deposited Graphene Films Using Inline XPS and Raman Metrology
Dominic Esan, Kitty Kumar, Ahmad Al-Kukhun, Wing-Shun Lam, Sisi Cao, GANESH VANAMU, Yinon Katz, Haim Prigozin, Lior Neeman, Tamar Hess, Sumegha Godara, Roland Barbosa – Intel
As semiconductor devices shrink below 2-nm, copper-interconnect reliability is growing constrained by electromigration and diffusion into surrounding dielectrics. Traditional capping layers such as Cobalt provide protection but add unwanted parasitic resistance and limit further scaling. Graphene offers a promising alternative due to its atomic thickness and high electrical conductivity. However, integration of graphene in the back-end-of-line stack requires protection of graphene structure from the downstream processing steps. This work studies the impact of plasma-assisted (DL1) and thermally-grown (DL2) dielectric thin films on the graphene composition, thickness, and hybridization states using VeraFlex (XPS) and Elipson (Raman) metrology tools, developed by Nova Ltd. Plasma deposition, which uses ion bombardment, can lead to significant damage to the surface. Here, we examine the extent of this effect in multiple scenarios. The Raman spectra reveals that the thermal DL2 layer deposited directly over Graphene had minimal impact on the Graphene’s spectrum, while a plasma DL1 layer changed significantly. The significant change in graphene quality by DL1 is evident from the drop of the 2D peak intensity, as compared to pristine graphene and graphene DL2 sample. On patterned wafers, the graphene quality deteriorates when exposed to the plasma deposition even when protected by one or few thermal layers. However, as the number of thermal layers increases, the extent of this damage diminishes, indicating DL2 can offer partial protection against plasma-induced damage. Complementary XPS analysis confirmed uniform deposition of both DL1 and DL2. Compared to the sp²/sp³ ratio derived from the C1s spectra of pristine graphene, DL1 processing leads to a reduction in the sp²/sp³ ratio, indicating increased disorder, whereas optimized DL2 layers restore a higher sp² fraction, consistent with reduced damage. Further, the results demonstrate uniform thermal DL2 growth and a clear correlation between DL2 thickness and graphene protection. These findings provide process-level insight into dielectric–graphene interactions and establish guidelines for integrating graphene with dielectric thin films in advanced interconnects.

P36. A Scalable Modeling of Void Defects in Monolithic Inter-tier Via
Yuqin Wang, Yajuan Su, Xiaojing Su, Pengyu Ren, Yujie Jiang, Zhanzi Chen, Tianao Chen, Fanqian Meng, Jiarong Yang, Yayi Wei – Institute of Microelectronics of Chinese Academy of Sciences
Monolithic inter-tier vias are key vertical interconnects in monolithic 3D integrated circuits, yet nanoscale void defects remain challenging to detect using existing test methods.A scalable analytical models precisely characterizing the parasitic parameters of Monolithic inter-tier vias with voids are firstly established in this paper. Results indicate that void defects induce measurable resistance increases and significantly impair transmission performance, providing a solid theoretical basis for high-sensitivity MIV defect detection.

P37. Modeling the Impact of Transition-Metal Dopants on ZnO Using Materials Studio and CASTEP
Rasool Akhtar Alias Osama, Hannah Levene, Graham Wood, Peter Lomax, Rebecca Cheung – The University of Edinburgh
The study employs first-principles calculations to investigate the doping of transition metals in the crystal structure of ZnO. The dielectric and conductive properties of the material are enhanced by the addition of these dopants. The changes of properties of ZnO in modeling is carried out by the use of Material Studio and simulation in CASTEP. In this study, the atoms of Manganese (Mn) and Indium (In) are replaced by the atoms of Zinc (Zn). Some of the aspects that we are interested in are the X-ray diffraction spectra, band structure and optical properties, including conductivity and dielectric function. The presented computational study is promising and can be used as an excellent source of information in experimental studies in the future.

P38. Materials and Device Design Rules for Voltage-Controlled Magnetism in MTJ-Compatible Stacks
Bhagwati Prasad, Astha Khandelwal, Ismat Jamil, Naveen Negi – Indian Institute of Science Bengaluru
Voltage-controlled magnetism provides a practical pathway to reduce write energy in MRAM-based memories by replacing dissipative current-driven switching with capacitive electric-field control. This paper consolidates our recent experimental evidence and device concepts into actionable design rules for three MTJ-compatible voltage-control routes: voltage-controlled magnetic anisotropy, voltage control of interlayer exchange coupling, and multiferroic magnetoelectric control. We translate reported benchmarks into stack-level guidelines covering interface chemistry, heavy-metal selection, spacer-layer sensitivity, gate dielectric choice, thermal budget constraints, imprint mitigation, and variability control. We further map these rules onto device architectures to highlight near-term manufacturable integration pathways for low-power, high-endurance spintronic memories.

THURSDAY, JUNE 4, 2026

8:15 – 8:55
Session 11: Keynote – Advanced Packaging Interconnect Scaling for Next-Generation AI Accelerators
Mark Kuemerle – Marvell Technology

Session 12: 3D Integration & Packaging II
Chair: TBD

8:55 – 9:20
12.1 Wafer Level System Integration [Invited]
Conrad Guhl, Fraunhofer IZM
Advanced packaging offers multiple options to improve system performance by high interconnect density and short connection length between different elements. In case of classical 2.5D packaging a substantial area of the interposer landscape is used by passive elements e.g. capacitors, resistors, inductors. Incorporation of such elements in the interposer itself as integrated passive devices (IPD) offers potential for further miniaturization and great reduction in interconnect distance between MPUs and passives from several mm to nm – µm.

Examples of R&D level interposer structures with integrated 3D capacitor and resistor elements will be presented. As all R&D activities are based on industry level 300 mm equipment, the results and the future extension are available for pilot tests. For such activities the capabilities of the European pilot line for advanced packaging and heterogeneous integration (APECS) will be presented.

9:20 – 9:40
12.2 Novel Temporary Bonding and Debonding Process based on 365 nm UV for Advanced Packaging
Abhaysinha Patil, Takuya Fukuda, Koen Kennes, Cuypers Dieter, Violeta Georgieva, Alain Phommahaxay, Gerald Beyer, Eric Beyne, Zsolt Tokei – IMEC
A new temporary bonding and debonding process using a photoactivated, thermally debondable release layer (RL) is introduced to assess ultra-thin die handling. Process flows like wafer-to-wafer and die-to-wafer bonding were used for concept validation. Plasma dicing of a thin silicon wafer on the temporary bonding system was chosen as die singulation technique and die release/handling was tested without the need of RL etch. We demonstrate direct die-to-wafer bonding (dD2W) as target process flow in which all dies were pick-and-placed from the temporary bonding system onto the target wafer without any damage using full automation. Finally, the die backside was cleaned and inspected for downstream processing.

9:40 – 10:00
12.3 Metal-Fill Free High-Aspect-Ratio Silicon-based Through Silicon Vias in Interposer
Alice Mo, Zachary Nelson, Luke Theogarajan – University of California, Santa Barbara
As through-silicon vias (TSVs) have become a key component of 2.5D and 3D integrated devices, there is an increasing need to improve TSV packaging processes to meet the demands of higher speeds and device performance. Metal-fill processes become increasingly difficult with higher via aspect ratios because of challenges in conformal deposition to the feature sidewalls and thermo-mechanical reliability. To simplify the via fabrication process and improve yield, degenerately doped silicon substrates can be etched to form high aspect ratio silicon TSVs without the need for a metal via fill. We demonstrate 21:1 aspect ratio silicon-based TSVs that decreases processing steps, reduces voids, and minimizes defect formation throughout the vias. Unlike metal-fill processes, the vias created with this technique retain the mechanical strength and stability of silicon while maintaining signal fidelity with a filled insulator. This characteristic enables simultaneous processing with other deep silicon etches including die slot definition and reduces etch processing times by half. Our approach demonstrates over 300 micron tall silicon pillars with low-k benzocyclobutene dielectric fill to form silicon-based TSVs in interposer with high aspect ratios, low defects, and ease of processibility.

10:00 – 10:20
12.4 Study on Enhancing Thermal Conductivity of AlN Thin Films for TSV Insulators in 3DICs and Chiplets by CM-CVD
Otaka, Yuhei; Lu, Yin-Chi; Hatakeyama, Daiki; Yamaguchi, Jun; Hirabaru, Tomoko; Arashida, Masao; Tamaoki, Naoki; Sato, Noboru; Tsukune, Atsuhiro; Shimogaki, Yukihiro – University of Tokyo
Three-dimensional integrated circuits (3DICs) and chiplets intensify local heat flux, making thermal management a key reliability limiter. In TSV structures, the dielectric liner is typically SiO2, whose low thermal conductivity constrains heat dissipation. Although AlN is an attractive replacement, TSV sidewalls require conformal deposition with high step coverage, making a CVD-type process with practical throughput essential under a strict post-process thermal budget (≤400 ºC). Here we study low-temperature AlN growth by flow-modulation CVD (FM-CVD), in which intermittent precursor delivery enhances adsorption and surface reactions, enabling dense and conformal films at reduced temperature. We systematically evaluated the dependence of thermal conductivity on process parameters (temperature, total pressure, modulation sequence timing, and flow conditions) and identified temperature-specific optimal windows. Pre-nitridation of the Si surface prior to AlN growth improved thermal conductivity, and higher thermal conductivity generally correlated with larger grain size estimated from XRD peak broadening (Scherrer analysis). Under optimized conditions at 500 °C, a total pressure of 2.2-2.4 Torr yielded a thermal conductivity as high as 8.7 W/m·K. Based on these trends, we provide integration-oriented guidelines to maximize thermal conductivity at ≤400 ºC and outline a path toward 10 W/m·K at 400 ºC for TSV-insulator applications.

10:20 – 10:40 Morning Coffee Break

Session 13: Patterning & Metrology
Chair: TBD

10:40 – 11:05
13.1 TBD [Invited]
Young Byun, ASM

11:05 – 11:25
13.2 Dual Direct Metal Etch for Reliable and Extendable Advanced BEOL Interconnect
Giulio Marti, Gilles Delie, Yanan Li, Yiting Sun, Serena Rollo, Davide Tierno, Bart Kenens, Alicja Lesniewska, Olalla Varela Pedreira, Yannick Hermans, Akhilesh Kumar Mandal, Ivan Erofeev, Vincent Renaud, Stefan Decoster, Chen Wu, Seongho Park – imec
We demonstrate a Dual Direct Metal Etch (DDME) integration scheme for fully self-aligned vias (FSAV) using EUV-Self-Aligned Double patterning (SADP) and direct Ru etch on 300 mm wafers. Earlier pillar-based FSAV approaches revealed two key manufacturability challenges: increased resistance after the Ru recess and high variability introduced during the final CMP step. The DDME flow reorganizes the sequence by performing gap-fill and CMP prior to via patterning, thereby isolating the underlying Mx layer from recess-induced damage and significantly improving process control. The revised integration maintains the advantages of direct Ru etch while suppressing recess-driven resistance increase and reducing CMP-related variability. Notably, the scheme is also compatible with advanced Mx+1 metallization options, including Ru PVD and epitaxial Ru, further broadening integration flexibility. First electrical and morphological results confirm improved via integrity and reduced variability at advanced metal pitches. These findings establish DDME as a promising and manufacturable multi-layer FSAV solution for future advanced interconnect technologies.

11:25 – 11:45
13.3 Electrical validation of high-NA single patterning insertion for 1.4nm node
Guillaume Schelcher, Marc Demand, Souta Nishimura, Bart de Wachter, Yusuke Wako, thiam arame, Kathleen Nafus, Kouta Furuichi, Etienne De Poortere, Cyrus Tabery, Victor M. Blanco Carballo – Imec
The Electrical validation of a CAR resist patterning process is demonstrated using single-exposure 0.55NA EUV lithography tool combined with a single damascene integration scheme. Preliminary results demonstrate promising combo yield performance for e-test structures up to ~25cm total field length at 28nm, 30nm and 32nm pitch.

11:45 – 12:05
13.4 Defectivity Propagation Study in MP18 Ru SID SADP Through e-Beam Inspection
Gilles Delie, Ganesha Durbha, Davide Tierno, Stefan Decoster, Evi Vrancken, Vincent Renaud, Mahmudul Hasan, Giulio Marti, Stéphane Lariviere, Roel Gronheid, Chen Wu, Seongho Park – imec
The imec roadmap predicts the need for a Cu alternative in the A10 node and beyond. Ru is poised to replace Cu due to several key properties. One of which is the possibility of a direct metal etch (DME) integration approach allowing for the inclusion of airgaps and other RC delay boosters. With the advent of high NA lithography 20 nm metal pitch and potentially 18 nm appear to be in reach for single patterning and direct etch. However, to keep pitch scaling possible, double patterning with a spacer-is-dielectric (SID) approach is required to allow for metal line width variations at small pitches. Such an approach requires a handful of pattern transfers and a pattern inversion step, increasing the likelihood of defect creation and propagation. Here we present a step-by-step defect inspection of large area structures using the eSL16TM e-beam inspection tool from KLA, to track the onset of defectivity and propagation through the process. Through identification of key defect-inducing process steps, process alterations are made to improve the yield.

Lunch Break
12:05 – 1:20

Session 14: Material & Process III
Chair: TBD

1:20 – 1:45
14.1 Advanced Memory Stacking: Thermal, Process and Reliability Challenges [Invited]
John Guzek, Micron

1:45 – 2:05
14.2 CMP Challenges in Dual Direct Metal Etch approach at 18-nm Pitch
Bart Kenens, Giulio Marti, Gilles Delie, Yanan Li, Yiting Sun, Serena Rollo, Davide Tierno, Alicja Lesniewska, Olalla Varela Pedreira, Yannick Hermans, Akhilesh Kumar Mandal, Ivan Erofeev, Vincent Renaud, Stefan Decoster, Chen Wu, Seongho Park – imec
A Dual Direct Metal Etch (DDME) integration scheme for MP18 Ru interconnects was developed to enable integration of low-resistive alternative conductors to overcome challenges in conventional Cu dual damascene process. The approach introduces two selective SiO2; CMP steps and a non-selective one requiring precise stopping behavior to prevent Ru damage, particularly for the low-density via layer. Optimized EP-based and timed CMP strategies demonstrate robust planarity, reduced within-wafer non-uniformity (WIWNU), and reliable via exposure, supporting scalable Ru interconnect fabrication.

2:05 – 2:25
14.3 Topological semimetal nanowires for post-copper interconnects
Nghiep Khoan Duong, Yeryun Cheon, Quynh P. Sam, Judy J. Cha – Cornell University
We report the synthesis and transport properties of three material candidates for post-copper interconnects: NbAs, CoIn3, and CuAl2. In the nanowire form, Weyl semimetal NbAs shows ~4X decrease in resistivity compared to the bulk, and its resistivity, thermal conductivity and breakdown current densities are on par with Co and Ru. The resistivities of CoIn3 and CuAl2 nanowires are higher than bulk values, owing to their off-stoichiometric compositions primarily due to vacancy formation. Our findings show topological Weyl semimetal NbAs is a leading alternative metal for next-generation interconnects.

2:25 – 2:45
14.4 Highly Oriented PVD Ru (002) Thin Films Enabled by an Ultra-Thin Ta Liner for Sub-2 nm Node Interconnects
Yusuke Mizobata, Kensei Kugio, Rozu Henmi, Sho Hamano, Kaito Tabata, Takahisa Tanaka, Munehiro Tada – Keio University
In this study, the effects of ultra-thin Ta adhesion liners (0.1-1.0 nm) inserted at the Ru/SiO2 interface are systematically evaluated in terms of adhesion, crystal orientation, and resistivity. A 0.2-0.3 nm thick Ta layer significantly enhances the high hcp(002) orientation of Ru, resulting in a resistivity of 13.0 µΩ·cm at the thickness of 20nm, which is lower than Ru thin film without adhesive liner (13.2 µΩ·cm), while keeping strong adhesion to SiO2. The ultra-thin Ta adhesion liner serves not only to ensure adhesion but also as an effective means of improving the crystallinity and (002) orientation of PVD Ru, thereby reducing the resistivity. This reduction compensates for the effective volume loss caused by the insertion of the Ta liner, making it a promising process approach for next-generation sub-2-nm-node interconnects.

2:45 – 3:05
14.5 Epitaxial growth of tetragonal CuAl2 as a conductor for high conducitivty internconnects (Cancelled)
Zahra Ahmadian, Atharv Jog, Nargess Arabchi, Ching-tzu Chen, D. Gall – Rensselaer Polytechnic Institute
Epitaxial tetragonal CuAl2(110) and CuAl2(001) layers with thicknesses d = 7–350 nm are deposited on MgO(001), with and without a TiN(001) wetting layer, to quantify the CuAl2 resistivity scaling and evaluate its potential as next-generation interconnect material. X-ray diffraction confirms phase-pure strongly oriented CuAl2 within a narrow stoichiometric window, while off-stoichiometric growth leads to polycrystalline films. Increasing the deposition temperature from T&#8347; = 100 to 300 °C results in a transition from two-domain CuAl2(110) epitaxy to single-crystal CuAl2(001) layers and a resistivity &#961; reduction from 8.14 to 6.39 &#956;&#937;-cm, reflecting suppressed electron scattering at domain walls in CuAl2(110) films. However, elevated temperatures T&#8347; &#8805; 300 °C lead to dewetting and discontinuous microstructures. TiN(001) nucleation layers improve wetting and facilitate &#961; vs d measurements, yielding a value for the &#961;o&#955; product for tetragonal &#952;-CuAl2 of (2.8 ± 1.2) × 10-15 &#937; m2.

3:05 – 3:25 Afternoon Coffee Break

Session 15: Contacts to CMOS Devices & Novel/Emerging Technologies II
Chair: TBD

3:25 – 3:45
15.1 Determining contact resistance at 42nm pitch of contact metal on highly doped Si:P in a shortloop flow
Philippe Marien, Karen Stiers, Gianluca Martini, Yannick Hermans, Tanushree Sarkar, Vincent Brissonneau, Heath Huang, Nicolas Jourdan, Matthias Vuurstaek, Bart Kenens, Jelle Vande Weeghde, Evi Vrancken, Sven Dewilde, Kevin vandersmissen, nancy heylen, Bart de Wachter, Yaksh Rawal, erik rosseel, Anjani Akula, Cassie Sheng, Gilles Delie, Chan BT, Juergen Boemmels, Maryamsadat Hosseini, Chen Wu, Seongho Park – imec
The contact area between the contact metal and channels S/D epi becomes smaller with advancing technology nodes. As a result, contact resistance starts to dominate the vertical resistance in a standard cell. A shortloop vehicle is required that is able to test contact resistance in a reliable and efficient manner. In that way, short feedback loops facilitate fast development of contact schemes with minimum resistance. In this paper, we present a shortloop vehicle to determine contact resistance measurements at 42nm pitch using a 65-step process flow. Additionally, we demonstrate its capability by comparing the impact of two different cleans on the contact resistance.

3:45 – 4:05
15.2 A Self-Aligned Monolithic CFET Architecture for CMOS Scaling beyond 10A
Qingpeng Wang, Yujia Zhong, Benjamin Vincent, Ivan Chakarov, Joseph Ervin – Lam Research Corporation
In this paper, we introduce a novel CFET architecture with multiple self-aligned processes for buried power rails (BPR), source drain contacts and back side through silicon via (TSV) contacts. We designed 6T SRAM cells and basic logic standard cells such as NOT, NAND and NOR gates employing this architecture. Using self-aligned processes, the SRAM and basic logic cells have a smaller cell area, while sharing similar or even greater patterning pitch. This self-aligned architecture can potentially support CMOS scaling beyond 10 A and address connection crowding issues expected in the development of next node devices.

4:05 – 4:25
15.3 Impacts of Contact Deposition Process and Interface Engineering on Monolayer WSe2 2D p-FETs
Tan, Yuanqiu; Yang, Shao-Heng; LIU, Haomin; Wan, Yi; Li, Lain-Jong; Appenzeller, Joerg; Chen, Zhihong – Purdue University, IBM Research
Contact engineering is one of the key challenges for complementary logic based on 2D semiconductors in ultra-scaled devices beyond silicon. This work reports a systematic study on the impact of the contact deposition process, metal choice, and interface engineering on monolayer WSe2 field-effect transistors (FETs). We demonstrate that DC sputtering of high work-function Ru enables a substantial enhancement in p-branch current compared to conventional evaporated metal stacks. In contrast, changing the metal work function alone is insufficient to overcome contact-limited device performance. We further show that inserting an ultrathin WOX interfacial layer provides additional improvement in hole injection efficiency. Statistical analysis across channel lengths ranging from 50 nm to 950 nm confirms that the performance enhancement is robust and uniform. These results underscore the critical role of process-aware interface engineering in enabling scalable p-type 2D transistors and provide a practical pathway for future ultra-scaled technologies.