2026 Workshop Agenda
2026 IITC Workshop Program MONDAY, JUNE 1, 2026
Thermal Management, Materials and Design
9:55 – 10:00 Welcome Andrew Kummel UCSD
10:00 – 10:45 KJ Cho, University of Texas at Dallas Nanophononics Interlayer Design of Heterostructure Thermal Boundary Resistance
The need for high power electronic devices are expanding for diverse applications including power conversion, smart grid, renewable energy generation and storage systems. The power capacity of a device is correlated to the bandgap of the semiconductors, and the performance of current GaN power devices is limited by the waste heat removal at the device level (8 W/mm compared to the electronic limit of 80 W/mm). Specifically, the thermal resistance along the heat transport pathway from the GaN device hot spots to an adjacent heat spreader (e.g., diamond) is dominated by the thermal boundary resistance (TBR) of the heterostructure interfaces. In this talk, we will discuss the role of nanoscale interlayers at the heterostructure interfaces and demonstrate that interlayer phonon engineering can enable novel phonon transport mechanisms at nanoscale leading to TBR values lower than the classical theoretical limit.
11:15 – 12:00 Satish Kumar, – Georgia Tech Machine Learning-Enabled Fast and Accurate Prediction of Thermal Properties via Thermo-Reflectance based Metrology
High power densities in 3D integrated circuits and heterogeneous integration technologies intensify hot spots, and demand precise thermal characterization to unlock effective thermal management strategies. The electronic materials confined to micro and nanoscale dimensions have thermal properties that can deviate significantly from bulk values. Optical metrologies, such as frequency-domain thermoreflectance (FDTR), time-domain thermoreflectance (TDTR), and transient thermoreflectance (TTR) are promising to measure thermal conductivities of these confined materials and thermal boundary resistances at their interfaces. Incorporation of machine learning models can rapidly infer thermal properties of interest from the experimental data, significantly improving accuracy, reducing computational overhead, and exhibiting robustness.
12:00 – 1:15 Lunch
1:15 – 2:00 Alfredo Bismuto, – META Design Considerations for Optimum Thermal Performance in AR/VR Application
Augmented and Virtual Reality devices present unique thermal challenges driven by the convergence of high-power optical engines, compact form factors, and proximity to the human body. This talk examines design strategies, simulation tools and workflows for managing thermo-mechanical loads across the optical stack — from display engines and waveguides to active dimming modules and lens assemblies — where even modest temperature excursions degrade image quality, accelerate material degradation, and impact user comfort. We discuss design trade-offs, thermo-opto-mechanical properties of the materials in eyepiece architectures, and present lessons learned from scaling AR glasses programs from prototype to high-volume manufacturing.
2:00 – 2:45 Stanley C Song, – Google Managing the Heat: Overcoming Thermal Bottlenecks in Backside Power Delivery
Backside Power Delivery is revolutionizing chip architecture by decoupling power and signal networks, but it introduces a critical challenge: severe thermal bottlenecks. By moving power grids to the wafer’s backside, conventional cooling paths are no longer applicable. This presentation explores advanced thermal management strategies, including innovative materials and design technology co-optimization. We analyze how to mitigate localized hotspots, ensuring next generation silicon delivers peak performance without ever becoming a significant heat source.
2:45 – 3:00 Coffee Break
3:00 – 3:45 Vladimir Noveski, – Micron Thermal challenges in HBM packaging
Advanced 2.5D and 3D-integrated memory systems face thermal limitations due to high power density at the HBM memory stack’s base and extended heat removal paths through layers with varying thermal resistance. Even with improved cooling, three challenges persist: (1) memory devices have lower thermal tolerance than logic; (2) the bottom logic die suffers from a highly resistive thermal path; and (3) localized hot spots risk device and data integrity. Advanced HBM and 3D architectures couple high-power xPU logic with insulative memory layers containing multiple BEOL dielectrics, especially when stacking multiple 3D cubes on a large xPU die.
This review paper will focus on the HBM thermal enhancements by package or DRAM silicon architecture change, and the key materials in the silicon and the package of the HBM product, and will also discuss the system level GPU/NPU/TPU environments and SIP level (COWOS) cooling solution roadmaps, but the same investigation and results will be discussed how they apply to 2.5D and 3D SIPs.
The memory architecture driven potential solutions are; 1) Thermal bumps and Thermal vias, 2) Hybrid bonding as improvement to solder based Thermal Compression Bonding (TCB), 3) Thermally conductive (TC) spacer / heat spreader integrated in the HBM package, 4) Logic die on the top of the stack, 5) integrate the HBM with SIP level new solutions such as immersion cooling, two phase cooling or microfluidic cooling solution.
In addition to architectural changes mentioned above, Micron plans also on evaluating low-CTE, high-modulus, high-thermal-conductivity dielectric materials such as aluminum nitride (AlN), diamond, and boron nitride (BN), which offer superior thermal transmission while maintaining electrical insulation (wide bandgap). The application of these materials will be discussed from the Silicon FEOL, BEOL to HBM memory package, but primarily will be applied as 1) interlayer dielectric as Al-O-N if possible to generate Ke=2.9-3.1 or less, 2) FS or BS Passivation layer, 3) Bonding layer for Hybrid bond, 4) gap fill material (replace MC).
3:45 – 4:15 Roundtable Discussion: Kummel (Chair), Bismuto, Song, Noveski, Kumar, Cho