Keynote #1 – Ken Rim – Corporate EVP, Samsung Electronics
“Scaling CMOS Technology beyond Nanometers”
Kern (Ken) Rim currently leads a leading edge logic technology development project at Samsung Electroncis. Before joining Samsung, he was with the process technology and foundry engineering organization at Qualcomm, where he collaborated with foundries in defining and productizing 10nm and 5nm technologies for mobile SoCs. He started his career at IBM Research focusing on transistor scaling and novel device structures, and later moved to IBM SRDC to participate in development and productization of multiple generations of CMOS technologies. He holds a BSE from Princeton and a PhD from Stanford in electrical engineering.
Abstract: CMOS scaling has maintained an astonishing rate of progress over decades, and technologists continue discovering ways to overcome barriers and extend logic technology nodes into the angstrom regime. Innovations that enable technology scaling have reached beyond MOSFET and metal wire scaling, into the realms of die level integration and system-technology co-optimization. This presentation will highlight examples of innovations that helped shape the logic technology roadmap in this decade, and will examine questions and challenges each approach faces today, in the hope that doing so will motivate even more innovative solutions by those in the audience.
Keynote #2 – Prabu Raja, Senior VP, Applied Materials
“From Microns to Nanometers: Overcoming the Challenges of Scaling Interconnects in Semiconductor Devices and Packages”
Dr. Prabu Raja is senior vice president leading the Semiconductor Products Group. He leads Applied’s semiconductor process equipment businesses and the global field organization.
Dr. Raja was previously group vice president and general manager of the Patterning and Packaging Group, where his strong product focus and customer relationships helped to grow market share across CVD, ALD, Etch and Selective Materials Removal.
Dr. Raja previously also served as corporate vice president and general manager for the Etch, MDP and ALD product groups, where he led his teams to win in key inflections such as metal gate. In June 2010, he was named an Applied Materials Fellow for his outstanding technical contributions.
Dr. Raja began his career at Applied in 1995 in PVD, leading the development of various products including Ionized Metal Plasma Ti/TiN products and the family of Encore Tantalum and Copper products. His work has resulted in wide customer penetration and a dominant PVD market share.
Dr. Raja holds a Ph.D. in Plasma Physics from the Indian Institute of Technology, Delhi and continued his research at the University of Iowa. He has numerous patents and publications”.
“Intermetallic Compounds as Alternatives to Copper for Advanced Interconnect Metallization”
“Airgap Integration on Patterned Metal Lines for Advanced Interconnect Performance Scaling”
“Stress-configurable 1D/2D nanodevices on waferlevel”
Woong Sun Lee
“7 years after the A10 processor, the ERA of Heterogeneous Integration”
Byeong Sung Kim
“Beyond Optical Scaling – Roles and Opportunities for DTCO in Angstrom-Scale Era”
“Recent advances on qualification and reliability of Cu/SiO2 to Cu/SiO2 hybrid bonds for 3D Integrated Circuits”
“BEOL-integrated ferroelectric RAM for advanced semiconductor technology nodes”
“Towards knowledge enhanced process models for semiconductor fabrication”
“A Holistic Approach to System Design Technology Co-Optimization for Deep Single Digit Nodes”
Leibniz Institute of Surface Engineering (IOM)
“Solution-processable molecular oxides for integrated memories”