Keynote #1 – Ken Rim – Samsung Electronics
“Scaling CMOS Technology beyond Nanometers”
Kern (Ken) Rim currently leads a leading edge logic technology development project at Samsung Electroncis. Before joining Samsung, he was with the process technology and foundry engineering organization at Qualcomm, where he collaborated with foundries in defining and productizing 10nm and 5nm technologies for mobile SoCs. He started his career at IBM Research focusing on transistor scaling and novel device structures, and later moved to IBM SRDC to participate in development and productization of multiple generations of CMOS technologies. He holds a BSE from Princeton and a PhD from Stanford in electrical engineering.
Abstract: CMOS scaling has maintained an astonishing rate of progress over decades, and technologists continue discovering ways to overcome barriers and extend logic technology nodes into the angstrom regime. Innovations that enable technology scaling have reached beyond MOSFET and metal wire scaling, into the realms of die level integration and system-technology co-optimization. This presentation will highlight examples of innovations that helped shape the logic technology roadmap in this decade, and will examine questions and challenges each approach faces today, in the hope that doing so will motivate even more innovative solutions by those in the audience.
Keynote #2 – Sundar Ramamurthy – Applied Materials
“From Microns to Nanometers: Overcoming the Challenges of Scaling Interconnects in Semiconductor Devices and Packages”
Dr. Sundar Ramamurthy is responsible for Applied’s business in wafer-level packaging, specialty semiconductors and epitaxy markets. In his role, he leads an integrated team across the company to fuel growth in some of the fastest growing markets in the semiconductor industry.
Over the past two decades, Dr. Ramamurthy and his team have delivered profitable growth for the corporation in multiple areas of semiconductor equipment technologies—rapid thermal processing, plasma doping, physical vapor deposition, atomic-layer and chemical vapor deposition of thin metal films. He led teams that commercialized 20+ new products to solve critical transistor and interconnect scaling challenges by introducing new materials and interface engineering solutions.
Dr. Ramamurthy joined Applied as a new college graduate in 1996. He holds a Ph.D. in materials science and engineering from the University of Minnesota and a bachelor of technology degree in metallurgical engineering from the Institute of Technology, Banaras Hindu University. He has authored or co-authored over 30 technical papers in peer-reviewed journals and has more than 30 patents granted or pending. He is an active mentor with the Miller Center in Santa Clara University for accelerating social enterprises.
“Intermetallic Compounds as Alternatives to Copper for Advanced Interconnect Metallization”
“Airgap Integration on Patterned Metal Lines for Advanced Interconnect Performance Scaling”
“Stress-configurable 1D/2D nanodevices on waferlevel”
Woong Sun Lee
“7 years after the A10 processor, the ERA of Heterogeneous Integration”
Byeong Sung Kim
“Beyond Optical Scaling – Roles and Opportunities for DTCO in Angstrom-Scale Era”
“Recent advances on qualification and reliability of Cu/SiO2 to Cu/SiO2 hybrid bonds for 3D Integrated Circuits”
“BEOL-integrated ferroelectric RAM for advanced semiconductor technology nodes”
“Towards knowledge enhanced process models for semiconductor fabrication”
“A Holistic Approach to System Design Technology Co-Optimization for Deep Single Digit Nodes”
Leibniz Institute of Surface Engineering (IOM)
“Solution-processable molecular oxides for integrated memories”
Mechanical BEoL Robustness Evaluation Using Variable Loading Strategies and Acoustic Emission Damage Monitoring