TECHNICAL PROGRAM FOR IEEE IITC 2020

Monday, October 5, 2020

Workshop

Tuesday, October 6, 2020

Session 1: Conference kick-off / Awards Program
Session 2: Plenary Session
Session 3: Advanced Interconnect 1
Session 4: Advanced Interconnect 2

Wednesday, October 7, 2020

Session 5: Welcome to Day 2
Session 6: Integration / Patterning
Session 7: DTCO
Session 8: RC Scaling
Session 9: Posters Session

Thursday, October 8, 2020

Session 10: Welcome to Day 3
Session 11: MOL Contacts
Session 12: Reliability
Session 13: Characterization

Friday, October 9 , 2020

Session 14: Welcome to Day 4
Session 15: 3D, Memory, and Novel System
Session 16: Beyond Cu
Session 17: Conference wrap-up and plans for 2021

**All times in pacific standard time.

October 5 6:00 AM Pacific TimeWorkshop: Model Your Way to a Better Backend Technologyhttps://event.on24.com/wcc/r/2663760/9CBEBBE48642C671667DA6451D07A4C2
October 6 6:00 AM Pacific TimeSessions 1-4https://event.on24.com/wcc/r/2663781/D6477B52DB7652556F37BB8A33F2409B
October 7 6:00 AM Pacific TimeSessions 5-8https://event.on24.com/wcc/r/2663789/E728345C13E9F0C6C067E4EA1EA782CB
October 7 12:10 PM Pacific TimeSession 9A: On Demand Poster Sessionhttps://event.on24.com/wcc/r/2663817/8398484924D0A7A506F57EE465328C74
October 7 12:10 PM Pacific TimeSession 9B: On Demand Poster Sessionhttps://event.on24.com/wcc/r/2663821/D93DACA2C86DB6AE2A963CD71865F83F
October 8 6:00 AM Pacific TimeSessions 10-13https://event.on24.com/wcc/r/2663796/5459EA9F97C8FE9EC85F64540AD3F83C
October 9 6:00 AM Pacific TimeSessions 14-17https://event.on24.com/wcc/r/2663804/D9CC4973D478FD0130EB91964EC6C302
Keynote Talks On Demand https://event.on24.com/wcc/r/2756882/351244D4723744312BB7B89BE4979C7C

Model Your Way to a Better Backend Technology
Workshop Program

MONDAY, OCTOBER 5

Workshop Chairs: Zhihong Chen (Purdue University) and Larry Zhao (Applied Materials)

In recent years, Moore’s law has been redefined to include beyond scaling and extended to include integration of heterogenous capabilities and power consumption reduction. It is clear that the focus of the semiconductor industry has been shifted from shrinking individual devices to integrating new functionalities onto the same chip. Introducing new materials to back-end-of-line processes and stacking or embedding memory transistors on top of logic transistors demands materials and device innovation; however, the performance of these new materials, processes and functionalities at the circuit and system level will not be clear until a large effort of integration has been undertaken.

In this workshop, leading scientists and innovators will review the modeling approaches used in industry and academia, providing a powerful means to predict the performance of continuous scaling and integration of new interconnects and memories on chip. They will also show benchmarking of various materials and device technologies.

06:00 – 06:15am
Welcome and Introduction

6:15 – 7:15
Nicholas A. Lanzillo, IBM Research
Simulation and Experimental Research on Scaled Interconnects:
Multi-scale Modeling of High-Performance Interconnects for Next-Generation Logic & AI

7:15 – 8:15
Daniel Gall, Department of Materials Science, Rensselaer Polytechnic Institute
The Interconnect Resistivity Challenge

8:15 – 08:45 Coffee Break + moderated Questions and Answers

8:45 – 9:45
Charles Dezelah, ASM
Molecules to Materials: Chemistry of ALD Precursors for Alternative BEOL Metals

9:45 – 10:45
Joseph Ervin, Lam Research
The Impact of Process Integration and Variations on RC Performance

10:45- 11:15 Coffee Break + moderated Questions and Answers

11:15 – 12:15
Azad Naeemi, Georgia Institute of Technology
Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices

12:15 – 13:15
Mario Gonzalez, Imec
Thermomechanical Challenges for Device Interconnect and Advanced Packaging

13:15-13:30 Final reflections and Workshop Ends

TUESDAY, OCTOBER 6

Session 1: Conference Kick-off and Awards Program

Session and Conference Chairs:
Paul Besser (ARM), Robert Socha (ASML) and Soo-Hyun Kim (Yeungnam University)

6:00 – 6:20
Welcome and 2019 Best Paper Awards

Session 2: Plenary Session

Session Chairs:
Robert Socha (ASML), Hui Jae Yoo, Intel Corporation and
Kuan-Neng Cheng (National Chiao Tung University), Soo-Hyun Kim (Yeungnam University),

6:20 – 7:10
2.1 Keynote – The Future of Compute: The Connected World meets the Interconnected Platform
Mike Mayberry, CTO and Sr. VP/GM of Technology Development, Intel Corporation
7:10 – 8:00
2.2 Keynote – Technology for 3D ICs
H.-S. Philip Wong, VP of Corporate Research, TSMC, Willard R. and Inez Kerr Bell Professor, Stanford University

8:00 – 8:30 Coffee Break, with open chat

Session 3: Advanced Interconnect 1

Session Chairs: Glen Wilk (ASM), Zsolt Tokei (imec)

8:30 – 9:00
3.1 Invited – Advanced Interconnects
Takeshi Nogami, IBM
9:00 – 9:25
3.2 Semidamascene Interconnects for 2nm node and beyond
Gayle Murdoch, imec
9:25 – 9:50
3.3 Thermodynamic Exploration of Co–Alloy Diffusion Barriers for Advanced Cu Interconnect
Yuki Yamada, Tohoku University, Japan
9:50 –10:15
3.4 Wafer Surface Control for Ru Capping on Cu interconnect
Hirokazu Aizawa, TEL

10:15 – 10:45 Coffee Break, with open chat

Session 4: Advanced Interconnect 2

Session Chairs: Axel Preusse (GLOBALFOUNDRIES), Kaoru Maekawa (Tokyo Electron Ltd)

10:45 – 11:15
4.1 Invited – Resistance Implications of Cu and Co Interconnect Fabrication Options
Jon Reid, Lam Research
11:15 – 11:40
4.2 Co-doped Ru liners for highly reliable Cu interconnects with selective Co cap
Koichi Motoyama, IBM
11:40- 12:05
4.3 Hybrid Metallization with Cu in sub 30nm Interconnects
Marleen H. van der Veen, imec
12:05 – 12:30
4.4 Design of Mechanically Reliable ULK Glasses
Karsu Kilic, Stanford University, USA

WEDNESDAY, OCTOBER 7

Session 5: Welcome to Day 2

Session Chair: Paul Besser (ARM)

6:00 – 6:10 Housekeeping and introduction to Day 2

Session 6: Integration / Patterning.

Session Chairs: Todd Ryan (Intel), Mark Zaleski (Micron)

6:10 – 6:40
6.1 Invited – 7 nm BEOL Integration and Qualification for Manufacturing
Jeong-Hoon Ahn, Samsung
6:40 – 7:10
6.2 Invited – BEOL Device Technology and Integration for Denser Function
Suman Datta, University of Notre Dame
7:10 – 7:40
6.3 Invited – Selective process to improve self alignment
Regina Freed, Applied Materials
7:40 – 8:05
6.4 A Study of Metal on Metal Multiple Patterning Scheme
James Hsueh-Chung Chen, IBM

8:05 – 8:35 Coffee Break, with open chat

Session 7: DTCO

Session Chairs: Xiaopeng Xu (Synopsys), Susumu Matsumoto (Tower Partners Semiconductor)

8:35 – 9:05
7.1 Invited – WITHDRAWN
8:35 – 9:00
7.2 Interconnect Design-Technology Co-Optimization for Sub-3nm Technology Nodes
Rogier Baert, imec
9:00 – 9:25
7.3 Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
Su-Chen Fan, IBM

9:25 – 10:25 Coffee Break, with open chat

Session 8: RC Scaling

Session Chairs: Stefan Schulz (TU-Chemnitz), John Zhu (Qualcomm)

10:25 – 10:55
8.1 Invited – A Comprehensive BEOL Performance Extraction Methodology
Nick Lanzillo, IBM
10:55 – 11:20
8.2 Modeling and Benchmarking Back End Of The Line Technologies on Circuit Designs at Advanced Nodes
Victor Huang, Georgia Institute of Technology, USA
11:20 – 11:45
8.3 Scaling Effects on Microstructure and Implication on resistivity of Co Nanointerconnects
Szutung Hu, Unversity of Texas at Austin, USA
11:45 – 12:10
8.4 Optimizing Interconnects RC Variability for Automotive Manufacturing using Novel Advanced Process Control
Kwang Sing Yew, Globalfoundries, Singapore

Session 9: On Demand Poster Session

Session Chairs: Luke Henderson (BASF Electronic Materials), Ming Li (Rambus)

12:10 – 13:30

9.1 Grain boundary scattering in Ru and Cu interconnects
Troels Markussen, Synopsys, Denmark
9.2 High-growth-rate atomic layer deposition of high-quality Ru using a novel Ru metalorganic precursor
Yohei Kotsugi, Tanaka Precious Metals, Japan
9.3 Comparative Study of the Growth Characteristics and Electrical Properties of Atomic-layer-deposited W Films Obtained from Newly Synthesized Metalorganic and Halide Precursor
Yujin Lee, Yonsei University, Korea
9.4 Possibility of Cu2Mg for Liner-Barrier Free Interconnects
Linghan Chen, Tohoku University, Japan
9.5 The structural origin of the minimum diffusion barrier thickness of ultara-thin TaNx
Toshihiro Kuge, Tohoku University, Japan
9.6 Self-Aligning Ruthenium Interconnects
Leslie Schlag, Fachgebiet Nanotechnologie, Technische Universität, Germany
9.7 An Ultra Energy-Saving Metal/Insulator/Metal Structure for One Selector-One RRAM
Po-Husn Chen, Chinese Naval Academy, Taiwan
9.8 Development of Spin-on Carbon Materials with High Planarization Performance for Multilayer Resist Process
Keisuke Kawashima, Mitsui Chemicals, Inc., Japan
9.9 Evaluation of local valence electron density and dielectric functions in metal interconnects using spatially resolved EELS spectra
Naohiko Kawasaki, Toray Research Center, Inc., Japan
9.10 Low Temperature Graphene-Capping BEOL Metal Technology
Jian-Zhi Huang, National Taiwan University
9.11 Study of adhesion for Cu/Ru(Zn) on dielectrics by an improved four-point bending measurement
Qu Xin-ping, Fudan University, China
9.12 Electrodeposition and electrical properties of Ni or Ni-Co alloy thin films
Takeyasu Saito, Osaka Prefecture University, Japan

SESSION 9B

9.13 3D Coin Integration for Realizing Next-Generation Flexible Electronic Systems
Sohail Faizan Shaikh, King Abdullah University of Science and Technology (KAUST), Saudi Arabia
9.14 Suppression of H2O absorption by hydrophobic-like surface of SiOx without Si-OH group
TETSUYA UEDA, AIST, Japan
9.15 The Precursor Adsorption Mechanism, Growth Characteristics and Electrical Properties of Plasma-Enhanced Atomic Layer Deposited Tungsten Films by Using Tungsten Chloride Precursors
Seunggi Seo, Yonsei University, Korea
9.16 Improving Ruthenium Polishing Through the use of Ceria Abrasives
Christopher Netzband, SUNY Polytechnic Institute, Albany, NY
9.17 Analysis of Extreme Pattern Density and Interconnects Routing Impacts on Via Open
Kwang Sing Yew, Globalfoundries, Singapore
9.18 The Effect of Oxygen Content of ITO Bottom Electrode on Degradation Characteristics of (Pb, La)(Zr, Ti)O3 capacitor
Takeyasu Saito, Osaka Prefecture University, Japan
9.19 Fundamental studies on the curing behavoir of porous CVD and spin-on dielectrics
Nicole Koehler, Technische Universitat Chemnitz, Germany
9.20 Compatibility study of low temperature PECVD SiOxNy thin films on polymer resist for image sensor applications
Fabien CHEVREUX, STMicroelectronics, France
9.21 Plasma-induced roughness and chemical modifications of TiN bottom electrode and their impact on HfO2-MIM properties
Sophia Rogalskyj, SUNY Polytechnic Institute, Tokyo Electron Technology Center of America
9.22 Atomistic Modeling to Engineer Ohmic Contacts between Monolayer MoS2 and Transition Metals
Kumar Prashant, Indian Institute of Technology, Hyderabad, India
9.23 Selective Metal Deposition to Decrease Cost and Increase Productivity
Robert Rhoades, Revasum Inc, CA
9.24 Electrochemical Analysis of Copper Damascene Plating Bath used for Direct Plating on Cobalt Barrier
Michael Pavlov, ECI, NJ

THURSDAY, OCTOBER 8

Session 10: Welcome to Day 3

Session Chair: Paul Besser (ARM)
6:00 – 6:10 Housekeeping and introduction to Day 3

Session 11: MOL Contacts

Session Chairs: Hiroyuki Nagai (Tokyo Electron Ltd), Dan Edelstein (IBM)
6:10 – 6:40
11.1 Invited – MOL/BEOL Intersection for Advanced CMOS Nodes
Oleg Gluschenkov, IBM
6:40 – 7:05
11.2 Material Innovation for MOL Contact Resistance Reduction with Selective Tungsten
Raymond Hung, Applied Materials
7:05 – 7:30
11.3 Nickel-Based CMOS-Compatible Contacts on P-InGaAs for III-V / Silicon Hybrid Lasers
Flore Boyer, STMicroelectronics, France

7:30 – 8:00 Coffee Break, with open chat

Session 12: Reliability

Session Chairs: Chris Wilson (imec), Mehul Naik (Applied Materials)

8:00 – 8:30
12.1 Invited – Interconnect Reliability
Kristof Croes, imec
8:30 – 8:55
12.2 Intrinsic Reliability Study in Low-k Dielectrics with Co Metallurgy in 10nm Process
Galor Zhang, Intel
8:55 – 9:20
12.3 In-situ Electrothermal TEM Investigation of Electromigration in fully Embedded Cu/Co Interconnects
Miji Lee, Samsung
9:20 – 9:45
12.4 Electromigration Void Behavior Revisited
Christian Witt, Globalfoundries

9:45 – 10:15 Coffee Break, with open chat

Session 13: Characterization

Session Chairs: Andrew Yeoh (Applied Materials), Gregory Imbert, STMicroelectronics

10:15 – 10:45
13.1 Invited – Characterization and Mitigation of EM Effects in Advanced Nodes
Chris H. Kim, University of Minnesota
10:45- 11:10
13.2 Characterization of interface interactions between Graphene and Ruthenium
Swati Achra, KU Leuven / imec, Belgium
11:10 – 11:35
13.3 Resistivity Impact from Modulated Line-Edge-Roughness with Self-aligned Double Patterning
Dewei Xu, Globalfoundries
11:35-12:00
13.4 Proximity Effect of Selective Co ALD on the Nanoscale
Michael Breeden, UC San Diego, USA
12:00-12:25
13.5 Impact of Surface Condition on Cobalt Drift into LK3.0 Films
Davide Tierno, imec

FRIDAY, OCTOBER 9

Session 14: Welcome to Day 5

Session Chair: Paul Besser (ARM)
6:00 – 6:10 Housekeeping and introduction to Day 5

Session 15: 3D, Memory, and Novel System

Session Chairs: Soo-Hyun Kim (Yeungnam University), Sanjeev Aggarwal (Everspin)

6:10 – 6:40
15.1 Invited – Computing Reimagined – AI for material, material for AI
Shintaro Yamamichi, IBM
6:40 – 7:10
15.2 Invited – Memory Technologies
Arnaud Furnemont, imec
7:10 – 7:35
15.3 Integration of an Advanced 3D TSV with the 7nm EUV Logic Process
SHAOFENG DING, Samsung
7:35 – 8:00
15.4 Impacts of Misalignment on 1um Pitch Cu-Cu Hybrid Bonding
Yoshihisa Kagawa, Sony

8:00 – 8:30 Coffee Break, with open chat

Session 16: Beyond Cu

Session Chairs: Kazuyoshi Ueno (Shibaura Institute of Technology), Mansour Moinpour (EMD Performance Materials)

8:30 – 9:00
16.1 Invited – Application of Supercritical Carbon Dioxide Fluids to Advanced Metallization
Eiich Kondoh, University of Yamanashi
9:00 – 9:25
16.2 Thickness scaling of NiAl thin films for alternative interconnect metallization
Jean-Philippe Soulié, imec
9:25 – 9:50
16.3 Enhanced Vertical Conductivity in Few-layer Graphene and Graphite with Transition Metal Intercalation: a Theoretical Study
Zeyuan Ni, TEL
9:50 – 10:15
16.4 Ru as an alternative material for advanced contacts
Maryamsadat Hosseini, imec
10:15 – 10:40
16.5 Structural Stability of Tight-Pitched Damascene Interconnects
Sagarika Mukesh, IBM
10:40 – 11:05
Paper 16.6
Fabien Roze,  Laser Systems & Solutions of Europe (LASSE)
11:05 – 11:30 Coffee Break, with open chat

Section 17: Conference wrap-up and Plans for 2021

Session Chairs: Paul Besser (ARM), Kuan-Neng Chen (National Chiao Tung University), and Kazuyoshi Ueno (Shibaura Institute of Technology)

11:30 – 12:00
Conference wrap-up
Plans for 2021