Model Your Way to a Better Backend Technology
Workshop Program


Workshop Chairs: Zhihong Chen (Purdue University) and Larry Zhao (Applied Materials)

In recent years, Moore’s law has been redefined to include beyond scaling and extended to include integration of heterogenous capabilities and power consumption reduction. It is clear that the focus of the semiconductor industry has been shifted from shrinking individual devices to integrating new functionalities onto the same chip. Introducing new materials to back-end-of-line processes and stacking or embedding memory transistors on top of logic transistors demands materials and device innovation; however, the performance of these new materials, processes and functionalities at the circuit and system level will not be clear until a large effort of integration has been undertaken.

In this workshop, leading scientists and innovators will review the modeling approaches used in industry and academia, providing a powerful means to predict the performance of continuous scaling and integration of new interconnects and memories on chip. They will also show benchmarking of various materials and device technologies.

06:00 – 06:15am
Welcome and Introduction

6:15 – 7:15
Nicholas A. Lanzillo, IBM Research
Simulation and Experimental Research on Scaled Interconnects:
Multi-scale Modeling of High-Performance Interconnects for Next-Generation Logic & AI

7:15 – 8:15
Daniel Gall, Department of Materials Science, Rensselaer Polytechnic Institute
The Interconnect Resistivity Challenge

8:15 – 08:45 Coffee Break + moderated Questions and Answers

8:45 – 9:45
Charles Dezelah, ASM
Molecules to Materials: Chemistry of ALD Precursors for Alternative BEOL Metals

9:45 – 10:45
Joseph Ervin, Lam Research
The Impact of Process Integration and Variations on RC Performance

10:45- 11:15 Coffee Break + moderated Questions and Answers

11:15 – 12:15
Azad Naeemi, Georgia Institute of Technology
Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices

12:15 – 13:15
Mario Gonzalez, Imec
Thermomechanical Challenges for Device Interconnect and Advanced Packaging

13:15-13:30 Final reflections and Workshop Ends