New dimensions to harness, upside & backside; what to consider and how to control?

Workshop Program

As the conventional planar scaling of CMOS devices reaches its limits, new directions are being pursued in the vertical dimension to achieve better power, performance, and area (PPA). This shift began with the development of device architectures such as FinFETs, Nanosheets, VTFETs, and StackFETs, which extend or stack up the transistor channels vertical direction. The trend is now expanding to the interconnect/BEOL domain, where the backside of the wafer (BSPDN) and the vertical stacking of semiconductor dies (HBM) are being explored. These vertical integration techniques enable new possibilities for chip design and packaging that can improve PPA. However, they also pose new difficulties in various aspects such as wafer distortion, metrology, defect control, heat management, and reliability. These difficulties must be addressed to ensure the quality and functionality of the devices with novel structures. One of the critical areas that requires more attention is the wafer bonding and thinning process, which affects the lithography process on the wafer backside. Another significant challenge is the heat removal of the bonded wafers that lack the Si substrate. In this workshop, experts from both industry and academia will present and discuss the key technical challenges in detail associated with the 3-dimensional integration of devices, so that the audience can gain more knowledge and insights on this new and important industry trend.

09:00 – 9:15am
Welcome and Introduction
By Kisik Choi, IBM Research

09:15 – 9:55am (+Q&A 5 mins)
BSPDN design considerations for advanced logic device
By Stanely S.C. Song, Google

10:00 – 10:40am (+Q&A 5 mins)
Delivering Power and Removing Heat; Two challenges that could become the Achilles heel for AI Applications
by Madhavan Swaminathan, Penn State University

10:45 – 11:15am
Coffee Break

11:15am – 11:55am (+Q&A 5 mins)
Advanced packaging solutions for high performance memory
By Kunal Parekh, Micron

12:00 – 13:00pm

13:00 – 13:40pm (+Q&A 5 mins)
Wafer bonding hybrid/fusion bonding
By Ilseok Son, TEL

13:45 – 14:25pm (+Q&A 5 mins)
Backside patterning from lithography perspective: alignment, metrology, and overlay control
By Michael Kubis, ASML

14:30 – 15:00pm
Coffee Break

15:00 – 15:40pm (+Q&A 5 mins)
Wafer warpage control by film deposition
By Fayaz Shaikh, LAM Research

15:45 – 16:30pm
Round Table Discussion

16:30 – 16:45pm
Final reflections

Workshop Ends

Welcome and Introduction: Kisik Choi, IBM Research

Kisik Choi has been leading the advanced interconnect integration team at IBM Research in Albany, New York since 2017. His team is focusing on the innovative technology development for the miniaturization of interconnect beyond 2nm. Before joining IBM, he contributed to the logic technology development for 32nm, 28nm, 14nm and 10nm including high-k/metal gate in SK Hynix, Globalfouondires, and AMD. He received the IEEE EDS George E. Smith Award in 2013 for his publication on HKMG. He was also awarded IBM’s Outstanding Technical Achievement Award in 2018. He is a senior member of IEEE and is currently serving on the IEEE IITC conference committee. He served as committee member for various conferences including AVS ALD conference and SEMICON Korea Technology Symposium. He has reviewed papers for multiple journals and proceedings and has over 90 publications and 100 patents. He received his M.S. and B.S. in Materials Science and Engineering from Seoul National University and his Ph.D. in Electrical & Computer Engineering from Texas Tech University.

Workshop Speaker #1: Stanely S.C. Song, Google

Back-side power delivery networks (BSPDNs) is one of key enablers of technology scaling, addressing on-chip power delivery, offering a multitude of benefits for logic devices, including reduced IR drop, increased signal routing freedom, and enhanced design flexibility. This workshop presentation will delve into the details of BSPDN design, including
• BSPDN Architectures and Implementation Options: Explore various BSPDN architectures, including Power Via, Tap Cell and Back Side Contact approaches with their implementation challenges and trade-offs.
• Impact on Logic Design, Performance, and Thermal Management: Insights into how BSPDNs influence logic design, performance metrics, and thermal considerations for High performance and mobile applications perspective.
• Design Tools, Methodologies, Reliability, and Testing: Understand the specialized design tools and methodologies tailored for BSPDN design, as well as reliability and testing strategies to ensure robust power delivery.

Stanley S.C. Song has been serving various technical and management roles in Si CMOS process, device and DTCO areas for several major semiconductor fab and fabless companies for more than 20 years, including Qualcomm, Samsung, Sematech and Texas Instruments. Currently he is at Google, and working on PPAC evaluation from RO and PD level for advanced technology nodes as well as n+1 and n+2 tech node pathfinding interacting with multiple levels of players in the semiconductor ecosystem. He received the Ph.D. degree in Electrical and Computer Engineering from The University of Texas at Austin.

Workshop Speaker #2: Madhavan Swaminathan, Penn State University

Heterogeneous Integration (HI) provides the opportunity for dense connectivity between smaller dies from advanced technology nodes to improve yield, provides for connectivity between optimized legacy technology nodes to reduce time to market, and enables the connectivity of dissimilar dies on a single platform to enhance functionality. With emerging applications in artificial intelligence (AI), the power delivery requirements are becoming astronomical while the thermal management solutions are becoming increasingly challenging. These two issues could very well become the Achilles heel for AI applications, unless appropriate solutions are sought and developed using HI.
This presentation will cover some of the emerging challenges in these areas along with solutions being pursued.

Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University. He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center.
Prior to joining Penn State University, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT). Prior to GT, he was with IBM working on packaging for supercomputers.
He is the author of 600+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He has won many awards with the most recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (highest award within the Electronics Packaging Society) for contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems.
He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Workshop Speaker #3: Kunal Parekh, Micron

The appetite for new applications in computing such as AI, automotive applications, and more efficient computing, are driving the need for memory and logic to rethink the architectures of both processing logic and memory, and resulting in new advanced packaging innovations that enable the future of 2.xD and 3D solutions. In this talk technology enabling interconnect and packaging and solutions will be discussed.

Kunal Parekh is a Sr. Director in Advanced Packaging Technology Development at Micron. His 30+ year career in the Semiconductor industry has provided him the opportunity to lead front end wafer Integration, development and manufacturing of DRAM, NAND, Phase Change Memory, and TSV for High Density Stacked Interconnects and HBM. He cofounded the IEEE EDS Chapter in Boise, the IEEE Workshop on Microelectronics and Electron Devices, and has served on the Symposium for VLSI Technology Committee. His contributions to innovation have resulted in over 250 US and foreign patents.

Workshop Speaker #4: Ilseok Son, TEL

Wafer bonding is one of key modules in 3DI/HI (3D Integration & Heterogeneous Integration) proving for a next generation scaling resolution path through BSPDN (Backside Power Delivery Network) & sequential CFET in logic, 3D Xtacking in NAND flash, multilayer stacking in HBM (High bandwidth memory). In this talk, wafer bonding type, process flow, and challenges in 3DI bonding will be introduced and TEL’s research work on the challenges will be discussed. This discussion covers wide range of topics including incoming wafer condition’s impact on bonding void & alignment, plasma surface activation modeling & yield impact, bonding alignment impact on e-test with 0.5um pitch hybrid bonding, Cu recess/ oxidation characterization & resolution, Cu anneal expansion modeling, improved bonding energy measurement method, and wafer distortion modeling.

Dr. Ilseok (Sunny) Son is the manager of 3DI & Heterogeneous Integration team in TEL Technology Center, America (TTCA) at Albany NY. Prior to joining TTCA in 2021, Sunny led NAND hybrid bonding team and R&D metrology team in SK Hynix to define resolution paths for next generation memory devices. He previously worked on 3DI technology and EUV at INTEL Component Research, and received Intel Achievement Award (IAA) from his work on 3DI research & development. Sunny obtained his PhD in Electrical Engineering from University of Wisconsin – Madison with specialty in MEMS.

Workshop Speaker #5: Michael Kubis, ASML

Lithography resolution has been driving dimensional scaling of semiconductor devices, but nowadays it is more and more complemented with device level 3D architectures (such as Gate-all-around) and system level 3D integration (such as stacked SRAM on Logic). Logic backside power delivery network (BS-PDN) is a disruptive innovation that offers significant performance gain in combination with higher transistor density. Key feature of this technology is the ability to connect to the already fully processed front-end devices from the backside. This connection takes place after fusion bonding and requires, depending on the chosen process flow, a single digit tight post-bonding scanner overlay control.
In this presentation, we will discuss implications of the BS-PDN processing on scanner alignment, overlay metrology, and overlay control for the post-bonding exposures. We will show that a significant improvement is possible to meet the overlay performance requirement by applying high order corrections per exposure of the scanner and we will discuss additional opportunities to improve the performance. We will pay special attention to the wafer edge (R > 135mm) as in this region it will be most challenging to achieve the required post-bonding overlay.

Michael Kubis has been working in the area of optical lithography and process control since 2001. He received his PhD in material science and solid state physics at the University of Technology in Dresden, Germany in 2000. He worked as Process Engineer and Senior Manager in Deep-Trench technology DRAM R&D and HVM of Infineon and Qimonda until joining ASML were he became System Engineer for on-product overlay applications. Since 2016, he is Senior Manager of System Engineering teams at ASML with special emphasis on metrology, patterning control, and technology roadmaps.

Workshop Speaker #6: By Fayaz Shaikh, LAM Research

While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.
Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 200 layers.
This talk will discuss the challenges of wafer shape/warpage in 3DNAND manufacturing and how backside engineering via deposition can solve and manage the wafer shape using VECTOR® DT.

Fayaz Shaikh is Sr. Director Engineering in PECVD Deposition Group in Lam Research. He has been working in semiconductor industry for more than 17 yrs. Throughout his tenure, he has held roles at Novellus and Lam Research in process engineering, software engineering, new product development, and product line leadership. During his process engineering roles he developed and released metal doped hard mask materials, developed a backside deposition product called VECTOR® DT for wafer warpage/bow management and compensation. This product has been instrumental in enabling 3DNAND scaling by allowing 100s of vertical layers. Additionally, this technology enables improved overlay performances for DRAM and Logic devices by allowing appropriate backside engineering of wafers.
He received his Master’s degree in Electrical and Computer Engineering from University of Alabama at Birmingham and PhD in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta. He enjoys solving problems, improving processes, and hitting slice shots in tennis.