Workshop Schedule for Monday, June 27, 2022:
06:00 – 06:15am
Welcome and Introduction
6:15 – 7:15
Nicholas A. Lanzillo, IBM Research
Simulation and Experimental Research on Scaled Interconnects:
Multi-scale Modeling of High-Performance Interconnects for Next-Generation Logic & AI
7:15 – 8:15
Daniel Gall, Department of Materials Science, Rensselaer Polytechnic Institute
The Interconnect Resistivity Challenge
8:15 – 08:45 Coffee Break + moderated Questions and Answers
8:45 – 9:45
Charles Dezelah, ASM
Molecules to Materials: Chemistry of ALD Precursors for Alternative BEOL Metals
9:45 – 10:45
Joseph Ervin, Lam Research
The Impact of Process Integration and Variations on RC Performance
10:45- 11:15 Coffee Break + moderated Questions and Answers
11:15 – 12:15
Azad Naeemi, Georgia Institute of Technology
Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices
12:15 – 13:15
Mario Gonzalez, Imec
Thermomechanical Challenges for Device Interconnect and Advanced Packaging
13:15-13:30 Final reflections and Workshop Ends
Workshop Speaker #1: John Park (Cadence)
Abstract: In the spirit of More-than-Moore, design teams are turning to advanced packaging techniques involving multiple chiplets to meet today’s demands of increased functional density, higher bandwidths and lower power products. Helping to accelerate this trend, the large IC foundries are now competing with the traditional packaging solution providers (OSATs) by providing their own back-end/packaging solutions based on wafer-level manufacturing techniques. The result is an explosion in the number of packaging technologies, pivoting the world of semiconductor packaging from a necessary evil to a value-add technology. From this presentation, you will learn about trends in advanced multi-chip(let) design, definitions to new terms like heterogenous integration, and challenges for package and IC designers when migrating to cutting-edge 2.5D and 3D packaging solutions.
Bio: John Park brings over 40 years of design and EDA experience to his role as Product Management Group Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysist
Workshop Speaker #2: Ganesh Subbarayan (Purdue)
Abstract: Heterogeneous Integration provides a powerful and cost-effective means for building complex Systems-in-Package (SiPs). Recently, sophisticated examples of heterogeneously integrated packages containing nearly 50 dies, many fabricated by different vendors on different technological nodes, have been demonstrated. In general, integration of large number of dies leads to a polynomial increase in material interfaces, which are potential locations for increased thermal resistance and mechanical fracture. Also, the larger sized multi-die packages result in complex chip-package interactions, while the smaller solder bump size results in joints that are largely made of brittle intermetallic compounds. In this talk, I will broadly describe the reliability concerns in heterogeneously integrated packages and illustrate through examples the thermo-mechanical behavioral characterization necessary for their reliability assessment. Specifically, I will describe (1) an assessment of stress induced by Through Silicon Vias (TSV) and its impact on mobility (2) the reasons for package-caused fracture in back-end-of-line (BEOL) structures (referred as chip-package interaction) (3) the effect of thermal expansion mismatch between the mold compound and silicon on fracture in BEOL structures and (4) modeling and experimental characterization of phase growth under current and elevated temperature (electromigration) in microbumps. Underlying the examples are sophisticated multiphysics computational models for moving (crack or phase) boundaries as well as fabricated test devices.
Bio: Ganesh Subbarayan is a Professor of Mechanical Engineering at Purdue University and the Co-Director of the Purdue-Binghamton SRC Center for Heterogeneous Integration Research in Packaging (CHIRP). He began his professional career at IBM Corporation (1990-1993). He holds a B.Tech degree in Mechanical Engineering (1985) from the Indian Institute of Technology, Madras and a Direct Ph. D. (1991) in Mechanical Engineering from Cornell University. Dr. Subbarayan’s research is broadly concerned with modeling and experimentally characterizing failure in microelectronic devices and assemblies. He was a pioneer in using geometric models directly for analysis, popularly referred to as Isogeometric Analysis. Among others, Dr. Subbarayan is a recipient of the 2005 Mechanics Award from the ASME EPP Division and the NSF CAREER award. He is a Fellow of ASME as well as IEEE, and he served as the Editor-in-Chief of IEEE Transactions on Advanced Packaging during 2002-2010.
Workshop Speaker #3: Muhannad Bakir (Georgia Tech)
Abstract: Monolithic ICs have progressed at an unprecedented rate of innovation in the past 60 years. But, due to performance, energy, and cost considerations, 2.5D and 3D ‘polylithic ICs’ have emerged as key enablers for the next phase of Moore’s Law. This presentation will discuss various emerging polylithic integration approaches using 2.5D and 3D IC technologies, including those being developed at Georgia Tech’s Integrated 3D Systems Lab. In particular, we first explore and benchmark scalable bridge-chip based 2.5D/3D IC technologies. Power delivery and thermal design considerations are also discussed and benchmarked for such technologies. Next, we discuss emerging 3D ICs technologies, including 3D Integrated Chiplet-Encapsulation (3D ICE), which enables the encapsulation of multiple chiplets using low-temperature SiO2 (ICP-PECVD) resulting in SiO2-reconstituted-tiers. Such reconstituted-tiers can then be stacked onto CMOS wafers to enable dense heterogeneous chiplet integration within BEOL. Lastly, we also discuss the possibility of using selective cobalt ALD deposition to form dense chip I/O bonds in 3D ICs. Unlike conventional bonding solutions, ALD-based chip bonding does not require any mechanical loads, is based on low-temperature processes, and has a higher-tolerance to surface imperfections in general.
Bio: Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir and his research group have received more than thirty paper and presentation awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one (best invited paper) from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded Best Paper Awards from the 2014 and 2017 IEEE Transactions on Components Packaging and Manufacturing Technology (TCPMT). Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. Dr. Bakir is the recipient of the 2018 IEEE Electronics Packaging Society (EPS) Exceptional Technical Achievement Award “for contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies.” He is also the co-recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Awards. In 2020, Dr. Bakir was the recipient of the Georgia Tech Outstanding Doctoral Thesis Advisor Award. He is also the recipient of several teaching awards, including the 2014 and 2015 Georgia Institute of Technology Class of 1940 Course Survey Teaching Effectiveness Award, and the 2020 Student Recognition of Excellence in Teaching: Class of 1934 Award. Dr. Bakir serves as a senior area editor of IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT) and was an Editor of IEEE Transactions on Electron Devices (TED) from 2014-2020.
Workshop Speaker #4: Garth Sunberg & Dandan Lyu (Ansys)
Abstract: Advanced simulation techniques and methodologies will be presented for the electromagnetic and signal integrity analyses of high-speed interconnects in 3DICs, silicon interposers and large chiplet-based SoCs. An EM-aware design flow will be discussed that aims to offer performance optimization of high-speed buses in the presence of power grid and package ground planes. A computational multiscale approach will be presented to link the information of mesoscale dissimilar solder ball geometries to the macroscale drop shock of a printed circuit board (PCB). A novel implicit incompressible smoothed particle Galerkin (ISPG) method is introduced to model the free-surface solder reflow process and predict the solder ball shapes. Subsequently, the predicted solder ball shapes from the reflow analysis are used in a chip package model for the drop shock analysis. The mesoscale solder joint model is coupled concurrently with the macroscale chip package model using an explicit-explicit non-intrusive two-scale coupling method via the co-simulation technique.
Bio:
Dr. Garth Sundberg received a B.S.E.E. and M.S.E.E from Oregon State University focusing on microwave engineering and compact modeling. Dr. Sundberg earned a Ph.D. in Electrical and Computer Engineering from Portland State University focusing on computational electromagnetics and remote sensing. Dr. Sundberg is a senior member of IEEE. Dr. Sundberg is a Senior Principal Engineer at Ansys where he works in many areas including signal and power integrity analysis, on-die electromagnetic extraction, electrical modeling of interposers, quantum computing, electrical and thermal modeling of packages and printed circuit boards, connector modeling, and radiated emissions modeling.
Dr. Dandan Lyu received her Ph.D. degree in Civil and Environmental Engineering from the University of California, Berkeley in 2018. Dr. Lyu joined Livermore Software Technology (LST), ANSYS after graduation. Dr. Lyu’s main research interests focus on multi-scale modeling including RVE analysis, two-scale co-simulation, data-driven material modelling and their applications in strucutal, electronics, and healthcare industries.
Workshop Speaker #5: Dan Jiao (Purdue)
Abstract: Heterogeneous Integration (HI) has shown tremendous potential to overcome the limitations and shortcomings of current monolithic integration technology, and effectively combat the slow-down of Moore’s law. Currently, HI is impeded by the lack of tools seamlessly integrated for system-level design automation and optimization, and it has become a bottleneck of the design flow. Unlike the design automation and optimization of on-chip design, the package and system design for HI remains largely manual, tedious, time consuming, non-optimal, and error prone. The design time from intent to finish for a complex system is unacceptably large, yet only a small fraction of the design space is explored. The design automation and optimization of HI is challenging because it must (1) simultaneously address the electrical, electromagnetic, optical, thermal, mechanical, and reliability challenges of integrating separately designed and manufactured components into a high-level system, (2) account for a diverse range of applications ranging from high-performance computing to autonomous vehicles, and hence vastly disparate integration needs and system requirements. In this talk, I will review the needs, challenges, key building blocks, and recent advances in multiphysics-informed design automation and optimization of HI.
Bio: Dan Jiao received her Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 2001. She then worked at the Technology Computer-Aided Design (CAD) Division, Intel Corporation until September 2005, as a Senior CAD Engineer, Staff Engineer, and Senior Staff Engineer. In September 2005, she joined Purdue University as an Assistant Professor with the School of Electrical and Computer Engineering, where she became a tenured Associate Professor in 2009, and a Full Professor in 2013. Prof. Jiao has authored over 300 papers in refereed journals and international conferences. Her current research interests include computational multiphysics, computational electromagnetics, design automation and optimization of integrated circuits and systems, applied electromagnetics, signal and power integrity, fast and large-scale numerical methods, etc. Prof. Jiao is an IEEE Fellow, an IEEE Distinguished Microwave Lecturer, a recipient of the Intel’s 2019 Outstanding Researcher Award, the 2013 S. A. Schelkunoff Prize Paper Award of the IEEE Antennas and Propagation Society, being one of the 85 selected for National Academy of Engineering’s (NAE) 2011 U.S. Frontiers of Engineering Symposium (FOE), the NSF Career Award in 2008, the Intel Logic Technology Development (LTD) Divisional Achievement Award in 2003, the 2000 Raj Mittra Outstanding Research Award, and a number of Best Paper Awards from conferences. Prof. Jiao serves as an Associate Editor of the IEEE Trans. on Components, Packaging, and Manufacturing Technology, the IEEE Journal on Multiscale and Multiphysics Computational Techniques, the IEEE Trans. on Microwave Theory and Techniques, and the IEEE Trans. on Signal and Power Integrity.
Workshop Speaker #6: Jeehwan Kim (MIT)
Abstract: For future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, needs for flexibility and stackability of electronic products have substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to the thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically complaint and less costly
than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-
crystalline inorganic materials. For the past half a decade, my research group at MIT has focused on mitigating such performance-mechanical compliance dilemma by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. In today’s talk, I will discuss about our strategies to realize such a dream electronic system [1-5] and how these strategies unlock new ways of manufacturing afvanced electronic systems [6-10]. I will highlight our 2D materials-based layer transfer (2DLT) technique that can produce single-crystalline freestanding membranes from any compound materials with their
excellent semiconducting performance. In addition, I will present unprecedented artificial heterostructures enabled by stacking of those freestanding 3D material membranes, e.g., world’s smallest vertically-stacked full color micro-LEDs [10], world’s best multiferroic devices [7], battery-less wireless e-skin [9,10], and
reconfigurable hetero-integrated chips with AI accelerators [8,10].
Bio: Prof.JeehwanKim’s group at MIT focuses on innovationsin nanotechnology for next generation computing and electronics.Prof. Kimjoined MIT in September 2015. Before joining MIT, he was a Research Staff Member at IBM T.J. Watson Research Center in Yorktown Heights, NY since 2008right after his Ph.D. He worked on next generation CMOS and energy materials/devices at IBM. Prof. Kim is a recipient of 20 IBM high value invention achievement awards. In 2012, he was appointed a “Master Inventor” of IBM in recognition of his active intellectual property generation and commercialization of his research. After joining MIT, he continuously worked nanotechnology for advancedelectronics/photonics. As its recognition, he received LAM Research foundation Award, IBM Faculty Award, DARPA Young Faculty Award,and DARPA Director’s Fellowship. He is an inventor of > 200 issued/pending US patents and an author of > 50 articles in peer-reviewed journals. He currently serves as Associate Editor of Science Advances, AAAS. He received his B.S. from Hongik University, his M.S. from Seoul National University, and his Ph.D. from UCLA, all of them in Materials Science.
Workshop Speaker #1: John Park (Cadence)
Abstract
Abstract: In the spirit of More-than-Moore, design teams are turning to advanced packaging techniques involving multiple chiplets to meet today’s demands of increased functional density, higher bandwidths and lower power products. Helping to accelerate this trend, the large IC foundries are now competing with the traditional packaging solution providers (OSATs) by providing their own back-end/packaging solutions based on wafer-level manufacturing techniques. The result is an explosion in the number of packaging technologies, pivoting the world of semiconductor packaging from a necessary evil to a value-add technology. From this presentation, you will learn about trends in advanced multi-chip(let) design, definitions to new terms like heterogenous integration, and challenges for package and IC designers when migrating to cutting-edge 2.5D and 3D packaging solutions.
Bio
Bio: John Park brings over 40 years of design and EDA experience to his role as Product Management Group Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysist
Workshop Speaker #2: Ganesh Subbarayan (Purdue)
Abstract
Abstract: Heterogeneous Integration provides a powerful and cost-effective means for building complex Systems-in-Package (SiPs). Recently, sophisticated examples of heterogeneously integrated packages containing nearly 50 dies, many fabricated by different vendors on different technological nodes, have been demonstrated. In general, integration of large number of dies leads to a polynomial increase in material interfaces, which are potential locations for increased thermal resistance and mechanical fracture. Also, the larger sized multi-die packages result in complex chip-package interactions, while the smaller solder bump size results in joints that are largely made of brittle intermetallic compounds. In this talk, I will broadly describe the reliability concerns in heterogeneously integrated packages and illustrate through examples the thermo-mechanical behavioral characterization necessary for their reliability assessment. Specifically, I will describe (1) an assessment of stress induced by Through Silicon Vias (TSV) and its impact on mobility (2) the reasons for package-caused fracture in back-end-of-line (BEOL) structures (referred as chip-package interaction) (3) the effect of thermal expansion mismatch between the mold compound and silicon on fracture in BEOL structures and (4) modeling and experimental characterization of phase growth under current and elevated temperature (electromigration) in microbumps. Underlying the examples are sophisticated multiphysics computational models for moving (crack or phase) boundaries as well as fabricated test devices.
Bio
Bio: Ganesh Subbarayan is a Professor of Mechanical Engineering at Purdue University and the Co-Director of the Purdue-Binghamton SRC Center for Heterogeneous Integration Research in Packaging (CHIRP). He began his professional career at IBM Corporation (1990-1993). He holds a B.Tech degree in Mechanical Engineering (1985) from the Indian Institute of Technology, Madras and a Direct Ph. D. (1991) in Mechanical Engineering from Cornell University. Dr. Subbarayan’s research is broadly concerned with modeling and experimentally characterizing failure in microelectronic devices and assemblies. He was a pioneer in using geometric models directly for analysis, popularly referred to as Isogeometric Analysis. Among others, Dr. Subbarayan is a recipient of the 2005 Mechanics Award from the ASME EPP Division and the NSF CAREER award. He is a Fellow of ASME as well as IEEE, and he served as the Editor-in-Chief of IEEE Transactions on Advanced Packaging during 2002-2010.
Workshop Speaker #3: Muhannad Bakir (Georgia Tech)
Abstract
Abstract: Monolithic ICs have progressed at an unprecedented rate of innovation in the past 60 years. But, due to performance, energy, and cost considerations, 2.5D and 3D ‘polylithic ICs’ have emerged as key enablers for the next phase of Moore’s Law. This presentation will discuss various emerging polylithic integration approaches using 2.5D and 3D IC technologies, including those being developed at Georgia Tech’s Integrated 3D Systems Lab. In particular, we first explore and benchmark scalable bridge-chip based 2.5D/3D IC technologies. Power delivery and thermal design considerations are also discussed and benchmarked for such technologies. Next, we discuss emerging 3D ICs technologies, including 3D Integrated Chiplet-Encapsulation (3D ICE), which enables the encapsulation of multiple chiplets using low-temperature SiO2 (ICP-PECVD) resulting in SiO2-reconstituted-tiers. Such reconstituted-tiers can then be stacked onto CMOS wafers to enable dense heterogeneous chiplet integration within BEOL. Lastly, we also discuss the possibility of using selective cobalt ALD deposition to form dense chip I/O bonds in 3D ICs. Unlike conventional bonding solutions, ALD-based chip bonding does not require any mechanical loads, is based on low-temperature processes, and has a higher-tolerance to surface imperfections in general.
Bio
Bio: Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir and his research group have received more than thirty paper and presentation awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE International Interconnect Technology Conference (IITC), and one (best invited paper) from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded Best Paper Awards from the 2014 and 2017 IEEE Transactions on Components Packaging and Manufacturing Technology (TCPMT). Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of Engineering Frontiers of Engineering Symposium. Dr. Bakir is the recipient of the 2018 IEEE Electronics Packaging Society (EPS) Exceptional Technical Achievement Award “for contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies.” He is also the co-recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Awards. In 2020, Dr. Bakir was the recipient of the Georgia Tech Outstanding Doctoral Thesis Advisor Award. He is also the recipient of several teaching awards, including the 2014 and 2015 Georgia Institute of Technology Class of 1940 Course Survey Teaching Effectiveness Award, and the 2020 Student Recognition of Excellence in Teaching: Class of 1934 Award. Dr. Bakir serves as a senior area editor of IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT) and was an Editor of IEEE Transactions on Electron Devices (TED) from 2014-2020.
Workshop Speaker #4: Garth Sunberg & Dandan Lyu (Ansys)
Abstract
Abstract: Advanced simulation techniques and methodologies will be presented for the electromagnetic and signal integrity analyses of high-speed interconnects in 3DICs, silicon interposers and large chiplet-based SoCs. An EM-aware design flow will be discussed that aims to offer performance optimization of high-speed buses in the presence of power grid and package ground planes. A computational multiscale approach will be presented to link the information of mesoscale dissimilar solder ball geometries to the macroscale drop shock of a printed circuit board (PCB). A novel implicit incompressible smoothed particle Galerkin (ISPG) method is introduced to model the free-surface solder reflow process and predict the solder ball shapes. Subsequently, the predicted solder ball shapes from the reflow analysis are used in a chip package model for the drop shock analysis. The mesoscale solder joint model is coupled concurrently with the macroscale chip package model using an explicit-explicit non-intrusive two-scale coupling method via the co-simulation technique
Bio
Bio:
Dr. Garth Sundberg received a B.S.E.E. and M.S.E.E from Oregon State University focusing on microwave engineering and compact modeling. Dr. Sundberg earned a Ph.D. in Electrical and Computer Engineering from Portland State University focusing on computational electromagnetics and remote sensing. Dr. Sundberg is a senior member of IEEE. Dr. Sundberg is a Senior Principal Engineer at Ansys where he works in many areas including signal and power integrity analysis, on-die electromagnetic extraction, electrical modeling of interposers, quantum computing, electrical and thermal modeling of packages and printed circuit boards, connector modeling, and radiated emissions modeling.
Dr. Dandan Lyu received her Ph.D. degree in Civil and Environmental Engineering from the University of California, Berkeley in 2018. Dr. Lyu joined Livermore Software Technology (LST), ANSYS after graduation. Dr. Lyu’s main research interests focus on multi-scale modeling including RVE analysis, two-scale co-simulation, data-driven material modelling and their applications in strucutal, electronics, and healthcare industries.
Workshop Speaker #5: Dan Jiao (Purdue)
Abstract
Abstract: Heterogeneous Integration (HI) has shown tremendous potential to overcome the limitations and shortcomings of current monolithic integration technology, and effectively combat the slow-down of Moore’s law. Currently, HI is impeded by the lack of tools seamlessly integrated for system-level design automation and optimization, and it has become a bottleneck of the design flow. Unlike the design automation and optimization of on-chip design, the package and system design for HI remains largely manual, tedious, time consuming, non-optimal, and error prone. The design time from intent to finish for a complex system is unacceptably large, yet only a small fraction of the design space is explored. The design automation and optimization of HI is challenging because it must (1) simultaneously address the electrical, electromagnetic, optical, thermal, mechanical, and reliability challenges of integrating separately designed and manufactured components into a high-level system, (2) account for a diverse range of applications ranging from high-performance computing to autonomous vehicles, and hence vastly disparate integration needs and system requirements. In this talk, I will review the needs, challenges, key building blocks, and recent advances in multiphysics-informed design automation and optimization of HI.
Bio
Bio: Dan Jiao received her Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 2001. She then worked at the Technology Computer-Aided Design (CAD) Division, Intel Corporation until September 2005, as a Senior CAD Engineer, Staff Engineer, and Senior Staff Engineer. In September 2005, she joined Purdue University as an Assistant Professor with the School of Electrical and Computer Engineering, where she became a tenured Associate Professor in 2009, and a Full Professor in 2013. Prof. Jiao has authored over 300 papers in refereed journals and international conferences. Her current research interests include computational multiphysics, computational electromagnetics, design automation and optimization of integrated circuits and systems, applied electromagnetics, signal and power integrity, fast and large-scale numerical methods, etc. Prof. Jiao is an IEEE Fellow, an IEEE Distinguished Microwave Lecturer, a recipient of the Intel’s 2019 Outstanding Researcher Award, the 2013 S. A. Schelkunoff Prize Paper Award of the IEEE Antennas and Propagation Society, being one of the 85 selected for National Academy of Engineering’s (NAE) 2011 U.S. Frontiers of Engineering Symposium (FOE), the NSF Career Award in 2008, the Intel Logic Technology Development (LTD) Divisional Achievement Award in 2003, the 2000 Raj Mittra Outstanding Research Award, and a number of Best Paper Awards from conferences. Prof. Jiao serves as an Associate Editor of the IEEE Trans. on Components, Packaging, and Manufacturing Technology, the IEEE Journal on Multiscale and Multiphysics Computational Techniques, the IEEE Trans. on Microwave Theory and Techniques, and the IEEE Trans. on Signal and Power Integrity.
Workshop Speaker #6: Jeehwan Kim (MIT)
Abstract
Abstract: For future of electronics such as bioelectronics, 3D integrated electronics, and bendable electronics, needs for flexibility and stackability of electronic products have substantially grown up. However, conventional wafer-based single-crystalline semiconductors cannot catch up with such trends because they are bound to the thick rigid wafers such that they are neither flexible nor stackable. Although polymer-based organic electronic materials are more compatible as they are mechanically complaint and less costly
than inorganic counterparts, their electronic/photonic performance is substantially inferior to that of single-
crystalline inorganic materials. For the past half a decade, my research group at MIT has focused on mitigating such performance-mechanical compliance dilemma by developing methods to obtain cheap, flexible, stackable, single-crystalline inorganic systems. In today’s talk, I will discuss about our strategies to realize such a dream electronic system [1-5] and how these strategies unlock new ways of manufacturing afvanced electronic systems [6-10]. I will highlight our 2D materials-based layer transfer (2DLT) technique that can produce single-crystalline freestanding membranes from any compound materials with their
excellent semiconducting performance. In addition, I will present unprecedented artificial heterostructures enabled by stacking of those freestanding 3D material membranes, e.g., world’s smallest vertically-stacked full color micro-LEDs [10], world’s best multiferroic devices [7], battery-less wireless e-skin [9,10], and
reconfigurable hetero-integrated chips with AI accelerators [8,10].
Bio
Bio: Prof.JeehwanKim’s group at MIT focuses on innovationsin nanotechnology for next generation computing and electronics.Prof. Kimjoined MIT in September 2015. Before joining MIT, he was a Research Staff Member at IBM T.J. Watson Research Center in Yorktown Heights, NY since 2008right after his Ph.D. He worked on next generation CMOS and energy materials/devices at IBM. Prof. Kim is a recipient of 20 IBM high value invention achievement awards. In 2012, he was appointed a “Master Inventor” of IBM in recognition of his active intellectual property generation and commercialization of his research. After joining MIT, he continuously worked nanotechnology for advancedelectronics/photonics. As its recognition, he received LAM Research foundation Award, IBM Faculty Award, DARPA Young Faculty Award,and DARPA Director’s Fellowship. He is an inventor of > 200 issued/pending US patents and an author of > 50 articles in peer-reviewed journals. He currently serves as Associate Editor of Science Advances, AAAS. He received his B.S. from Hongik University, his M.S. from Seoul National University, and his Ph.D. from UCLA, all of them in Materials Science.