Model Your Way to a Better Backend Technology
Workshop Program

In recent years, Moore’s law has been redefined to include beyond scaling and extended to include integration of heterogenous capabilities and power consumption reduction. It is clear that the focus of the semiconductor industry has been shifted from shrinking individual devices to integrating new functionalities onto the same chip. Introducing new materials to back-end-of-line processes and stacking or embedding memory transistors on top of logic transistors demands materials and device innovation; however, the performance of these new materials, processes and functionalities at the circuit and system level will not be clear until a large effort of integration has been undertaken.

In this workshop, leading scientists and innovators will review the modeling approaches used in industry and academia, providing a powerful means to predict the performance of continuous scaling and integration of new interconnects and memories on chip. They will also show benchmarking of various materials and device technologies.

09:00 – 9:15am
Welcome and Introduction

09:15 – 9:55am (+Q&A 5 mins)
Nicholas A. Lanzillo, IBM Research

Multi-scale Modeling of High-Performance Interconnects for Next-Generation Logic & AI
Interconnect performance and reliability in advanced CMOS technology modes depends on many factors, including but not limited to structure, materials, process innovation and architecture. A global view of these critical factors is essential for proper design technology co-optimization (DTCO). I will discuss a multi-scale simulation strategy for interconnect performance assessment, building up from ab initio insights into materials and interfaces to circuit-level and block-level benchmarking. Distinctions between high-performance and mobile applications will be highlighted, as well as the enablement of interconnects for advanced memory and AI compute.

10:00 – 10:40am (+Q&A 5 mins)
Daniel Gall, Department of Materials Science, Rensselaer Polytechnic Institute

The interconnect resistivity challenge
The effective resistivity of conventional Cu interconnect lines increases by more than two orders of magnitude as their width decreases from 30 to 6 nm. Alternative metals have the potential to mitigate the resulting resistivity bottleneck by either (a) facilitating specular electron interface scattering and negligible grain boundary reflection or (b) a low bulk mean free path that renders resistivity scaling negligible. However, classical models provide no insight for achieving either (a) or (b). In contrast, first-principles transport simulations yield quantitative insight into (1) the requirements for specular surface scattering based on localized density of states, (2) grain boundary transmission coefficients based on Fermi-surface matching and interface potential, (3) direct metal performance comparisons based on calculated bulk mean free paths, and (4) resistivity scaling at <10 nm length scales where classical models completely fail due to quantum confinement. The modeling results are directly compared to experimental measurements from epitaxial thin films, yielding quantitative data on the most conductive metals for narrow interconnect lines.

10:45 – 11:15am
Coffee Break

11:15am – 11:55am (+Q&A 5 mins)
Charles Dezelah, ASM

Molecules to Materials: Chemistry of ALD Precursors for Alternative BEOL Metals
As interconnect dimensions continue to shrink, the need for alternative metals that provide low electrical resistivity and acceptable levels of electromigration is of increasing importance. This is especially true for the narrowest metal interconnects, where the effective resistivity can be considerably higher than observed in the bulk and where increased current densities can drive electromigration. In this presentation, candidate materials for next generation BEOL metallization will be discussed and chemical aspects of precursor selection and design will be described. In particular, attention will be given to surface chemical reactions, film growth mechanisms, modelling, and the impact of precursor characteristics on the properties of the resulting films. Examples will include ALD and CVD precursor chemistries for Co, Ru, Mo, and Ir, the role of the ligand and metal oxidation state in the control of film composition, morphology, nucleation, conformality, and electrical properties. Novel materials including binary and ternary conductive materials and their respective ALD precursor chemistries will also be considered.

12:00 – 13:00pm
Lunch

13:00 – 13:40pm (+Q&A 5 mins)
Joe Ervin, Lam Research

The impact of process integration and variations on RC performance)
Introducing new materials and process steps to back-end-of-line interconnects can be quite challenging, due to shrinking process windows at advanced technology nodes.    Resistance and capacitance budgets (and acceptable windows) decrease as a non-linear function of process dimension.    Nominal or expected variability for a specific process step might create unacceptable RC device performance when used in conjunction with a new integrated process sequence.   The interactions of these process steps and their variability, and the ultimate effect on yield, can be non-intuitive and difficult to visualize in advance.   We will demonstrate a modeling methodology that can be used to determine the impact (in advance) of process integration and variability on RC performance.   The methodology can not only be used to estimate RC device performance under varying material and process dimension assumptions, but to identify optimal process parameter ranges.

13:45 – 14:25pm (+Q&A 5 mins)
Azad Naeemi, Georgia Institute of Technology

Interconnect Technology Optimization for Conventional and Emerging Nanoscale Devices
In this talk, the implications of device characteristics on interconnect technology, design, and optimization is discussed, providing a holistic view of the impact of device innovation on interconnects, PPA, and reliability. Adapting interconnects to suit the device properties further enhances the circuit- and system-level performance. The FinFET-based designs are more sensitive to the interconnect resistance than the interconnect capacitance. Capturing the device and wire interactions, early co-optimization, and accurate wire length modeling is required for future technology pathfinding.

14:30 – 15:00pm
Coffee Break

15:00 – 15:40pm (+Q&A 5 mins)
Mario Gonzalez, Imec

Thermomechanical challenges for device interconnect and advanced packaging
The advancements in technology and materials enabling high density interconnections levels open new possibilities for 3D applications to complement the classic technology node scaling. However, thermal management and structural stability are becoming more critical for highly scaled devices and advanced packaging architectures. Deformations of solder joints, cracks in local metal interconnects and dielectric layers together with the warpage of the electronic packaging are still major reliability challenges originated by high induced thermal stresses.
The understanding of the factors that underlie the critical failures or the variation in performance of the integrated circuit requires accurate experimental measurements and simulation techniques performed to locate and quantify the stress levels that leads to the failure. Standard finite element method (FEM) is challenging due to the large dimensional difference between the packaging and interconnect structures. For this reason, sub modeling techniques are used to simulate the package induced stresses at different dimensional scales of the package. In this talk we will give an overview of numerical and experimental methodologies that can be used to simulate and characterize the Chip Package Interaction (CPI).

15:45 – 16:30pm
Round Table Discussion

16:30 – 16:45pm

Final reflections


16:45pm
Workshop Ends