One Day Workshop
“Interconnect Challenges for Next Generation Computing” on Monday, May 22nd, 2023.
Workshop Schedule for Monday, May 22, 2023
10.15 – 10.30
10.30 – 11.15
Non-volatile memory-based artificial synaptic devices for neuromorphic computing
Prof. Tae-Sik Yoon (UNIST, Korea)
Q & A Time
11.15 – 12.00
Embedded NVM for AI – Which memory is going to make the race?
Dr. Sven Beyer (GLOBAFOUNDRIES Fab-1, Germany)
Q & A Time
12.00 – 13.30
Break for Lunch
13.30 – 14.15
Si photonics for optical interconnects
Prof. Takenaka (University of Tokyo, Japan)
Q & A Time
14.15 – 15.00
Enabling Technologies for CMOS near fabrication of next generation devices
A research Fab perspective
Marcus Wislicenus (Fraunhofer IPMS, Germany)
Q & A Time
15.00 – 15.30
15.30 – 16.15
Interconnects for 3D integration of quantum technologies
Candice Thomas, Ph.D. (CEA-LETI, France)
Q & A Time
16.15 – 17.00
Quantum computing using NV centers
Prof. Jan Meijer (Uni Leipzig, Germany)
Q & A Time
17.00 – 17.15
18.30 – 21.30
Workshop, Keynote and Invited Speaker & Committee Reception
Workshop Speaker #1: Prof. Tae-Sik Yoon (UNIST, Korea)
The artificial synaptic devices are essential elements to develop brain-inspired neuromorphic computing systems. Unlike conventional von Neumann systems facing limitation in advance of their performance and suffering from heavy traffic issue in data transferring called von Neumann bottleneck, the neuromorphic systems using artificial synapse and neuron circuits have advantages such as high energy efficiency in operations, superior processing capability particularly for unstructured data, and so on. The artificial synapses in neuromorphic systems perform signal processing and consequently update their synaptic weight for learning and memory operations, which alleviates the delay issues in data-transfer that occur in von Neumann systems. In this talk, various non-volatile memory-based synaptic devices developed for use in artificial synapses to date will be discussed.
Tae-Sik Yoon, Ph.D. is a professor at Graduate School of Semiconductor Materials and Devices Engineering & Department of Materials Science and Engineering and Director of Center for Future Semiconductor Technology at Ulsan National Institute of Science and Technology (UNIST), Korea. Before joining UNIST, he was a professor in Myongji University from 2007 to 2020. After he received B.S., M.S., and Ph.D. degrees from Seoul National University, Korea, he was a postdoctoral researcher in Seoul National University and UCLA. Then, he worked for Samsung Electronics as a senior research to develop NAND flash memory devices. He has published around 130 journal papers and 15 patents. He was awarded a ministerial commendation from Ministry of Science and ICT for the contribution to semiconductor technology development at 2020. His current research interests include non-volatile memory devices and artificial synapse devices for neuromorphic systems.
Workshop Speaker #2: Dr. Sven Beyer (GLOBAFOUNDRIES Fab-1, Germany)
With ESF3 eFlash stalling cost-scaling in the 28nm node, BEoL-based emerging memories like PCRAM, RRAM & MRAM being manufacturing ready in 28/22nm and HfO2 based ferroelectric memories standing at the doorstep, it becomes a tough call on which horse to bet, when it comes to novel AI computing.
Commercial benefits of eNVM-based novel AI-architecture over CMOS tensor-based brute force compute, stored in maximum density SRAM, is yet to be proven. But “AI” is a large field, where uncountable ways are to be explored and, in the end, may offer a shortcut to Rome.
To harvest the benefits of eNVM, teams must work across the full “AI-layer stack”, starting from the application, over the neuromorphic algorithm, the programming language, the system software, the micro architecture, the PDK and Logic, down to the devices, where the well-chosen eNVM solution might make the final difference.
In this talk we will look at the status and applicability of available eNVM solutions for the use of neuromorphic computing.
Sven Beyer received his masters and Ph.D in Physics from the University of Hamburg, Germany. He started his career with Infineon as a manufacturing engineer in the etch department in 2003. He joined the integration department of AMD in 2005. He has spent a year in the ASTA alliance 2007 working on the 45nm node and has worked in many roles since then, lasting throughout the separation of GLOBALFOUNDRIES and AMD. Today he serves as DMTS in GLOBALFOUNDRIES FAB1, overseeing mainly the eNVM roadmap and development in Dresden.
Workshop Speaker #3: Prof. Takenaka (University of Tokyo, Japan)
Optical interconnects will become even more important for next-generation computing as the increase in I/O bandwidth makes power consumption more dominant for ultra-high-speed I/O interfaces. Si photonics, which enables a large scale photonic integrated circuit on a Si platform using the CMOS compatible process, is expected to be a key enabler for high density, high speed and low power optical interconnects integrated with CPUs and GPUs. In this talk, we will review state-of-the-art Si photonics technologies including lasers, modulators, photodetectors, and other devices, as well as advanced integrated systems for optical interconnects.
Mitsuru Takenaka received his B.E., M.E., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1998, 2000, and 2003, respectively. During 2003-2007, he was a research fellow of the Optoelectronics Industry and Technology Development Association, where he was engaged in research on photonic routers. In 2007, he joined the Department of Electrical Engineering, the University of Tokyo, as a lecturer. In 2008, he became an associate professor at the Department of Electrical Engineering and Information Systems, the University of Tokyo. Since 2020, he is a professor at the Department of Electrical Engineering and Information Systems, the University of Tokyo. His research interests presently focus on the heterogeneous integration of III-V/Ge/2D materials on a Si platform for electronic-photonic integrated circuits. Dr. Takenaka is a member of IEEE Photonics Society, IEEE Electron Devices Society, Optical Society of America, the Institute of Electronics Information, and Communication Engineers (IEICE), and the Japan Society of Applied Physics (JSAP).
Workshop Speaker #4: Marcus Wislicenus (Fraunhofer IPMS, Germany)
Introducing new materials and building up unconventional processing paths are key to delivering both interconnect performance boost for future technology nodes and enabling the production of next generation devices.
Alongside the stepwise replacement of Copper at smaller dimensions by materials with superior properties, the continuous improvement of the legacy tool set pushes the foreseen limits of the more mature technology, keeping it the material of choice for the majority of applications.
Here, insights about new material introduction as well as tool upgrades within a research fab line will be presented.
Furthermore, examples for technology convergence enabling the fabrication of new devices are discussed. Inter alia, an integration concepts call hybrid metal fill and the enablement of ultra-long fine pitch interconnects are shown.
Marcus Wislicenus received the B. Eng. degree in microsystems technology and his M. Eng. degree in nano- and surface technologies from the University of Applied Science Zwickau, Germany in 2010 and 2013, respectively. In 2013 he joined the interconnects group of the Fraunhofer Institute for Photonic Microsystems IPMS, Dresden taking care of the multiscale investigation of advanced concepts for the back-end-of-line dual damascene metallization. Since 2019 he is leading the High Performance Technology group with an focus on enabling CMOS near quantum technologies. He provides expertise on PVD, CVD and ECD deposition, inline characterization (e.g. 3D-AFM, AR‐XPS, REELS) and resistivity modelling.
Workshop Speaker #5: Candice Thomas, Ph.D. (CEA-LETI, France)
I will present a Si-based interposer designed for the hybridization and three-dimensional integration of spin qubit arrays and cryo-CMOS control electronics chips. This interposer comprises interconnects made from conducting and superconducting materials to optimize the electrical connections between the qubit and control electronics circuits as well as the thermalization of the whole system. Fabrication of the different interconnects, using 200 mm silicon wafer technologies, will be reported with morphological characterizations. Electrical qualification of these interconnects within spin qubit operating conditions, in terms of temperature and magnetic field, will be discussed.
Dr. Candice Thomas received her Ph.D. degree from University Grenoble Alpes, France, in 2016. Between 2017 and 2019, she was a postdoctoral research associate at Microsoft Quantum Purdue in the USA, designing and growing hybrid superconductor-semiconductor hetero-structures for topological quantum computation. She then joined CEA-Leti in 2019, where she is now focusing on 3D integration and cryo-packaging solutions for silicon spin qubits.
Workshop Speaker #6: Prof. Jan Meijer (Uni Leipzig, Germany)
Defect centres in materials with large bandgaps, especially in diamond and SiC, have proven to be excellent candidates for so-called qubits in quantum information and sensing. Ion implantation is essential here, as it is the only way to produce qubits with high lateral resolution inside materials like diamond. In the talk, the techniques of focused single ion implantation will be discussed and we will present a quantum computer design that is based on this technology.
Prof. Meijer studied physics and astronomy at the University of Münster and received his doctoral thesis at the University of Bochum. In 2004 he became the managing director of the accelerator and isotope laboratory at Bochum. In 2013, he accepted the call of the University of Leipzig to a professorship in the Applied Quantum Systems Department. The main focus of Prof. Meijer work is the deterministic implantation and assembling of single ions with lateral resolution of a few nanometers.