Poster Session and Conference Reception (5:30 – 8:00)

Posters
Chairs: Fumihiro Inoue (Yokohama National University) & Chris Wilson (IMEC)

P1. Redefining 2-Level Semi-Damascene Interconnect Technology: Benchmarking three different Fully Self-aligned Via options

Giulio Marti, Gilles Delie, Gayle Murdoch, Anshul Gupta, Souvik Kundu, Stefan Decoster, Olalla Varela Pedreira, Alicja Lesniewska, Yannick Hermans, Bart Kenens, Fulya Ulu Okudur, Seongho Park, Zsolt Tokei – IMEC

This study highlights the effectiveness of a novel two-metal-level semi-damascene integration approach using fully self-aligned pillar-vias (FSAV) for interconnects ranging from 18 to 26 nm metal pitch. We employ EUV-SADP-SIM patterning scheme and direct metal etch of Ru to demonstrate the proof of concept on 300 mm wafers on 300mm wafers. This integration not only gives lower via resistance than the previously reported schemes but also promise lowers capacitance between the two metal layers. Furthermore, it significantly widens the via litho and etch process window, making it more attractive for advanced semiconductor manufacturing.

P2. Self-aligned 8nm T2T as cell boundary in the middle-of-line

Philippe Marien, Yannick Hermans, Subhobroto Choudhury, Souvik Kundu, Stefan Decoster, Fulya Ulu Okudur, Naveen Reddy, Bart Kenens, Nicolas Jourdan, Gilles Delie, Giulio Marti, Chen Wu, Victor Vega Gonzalez, Gayle Murdoch, Seongho Park, Zsolt Tokei – IMEC

In order to achieve tight, 8 to 12 nm cell boundaries, Ru direct metal etch can be used to split a larger via into two opposite facing smaller vias and create a tight metal line tip-to-tip (T2T) at the cell boundary. This is obtained by self-aligning the Ru direct metal etch to the tightest metal layer above. This technique of splitting a via and creating a T2T with zero line extension is promising for cell boundary definition of complementary FET. In this work, we will discuss lithography overlay and via CD process window definition to achieve the improved morphological and electrical results. For 8 nm T2T, we have obtained a 55% leakage current yield. Additionally, for 10 and 12 nm T2T, a leakage current yield of above 90% was achieved.

P3. Demonstration of MP18-26nm Ru Semi-Damascene Spacer-is-Dielectric SADP Integration

Chen Wu, Stefan Decoster, Vincent Renaud, Yannick Hermans, Philippe Marien, Giulio Marti, Nancy Heylen, Bart Kenens, Syamashree Roy, Fulya Ulu Okudur, Quoc Toan Le, Naveen Reddy, Alfonso Sepulveda Marquez, Gilles Delie, Anshul Gupta, Alicja Lesniewska, Gayle Murdoch, Seongho Park, Zsolt Tőkei – IMEC

This work presents a novel Spacer-is-Dielectric (SID) SADP Ru semi-damascene integration scheme by using metal-based core and gap hard masks. More than 70% yield in tested line resistance and line-to-line leakage, especially in MP18 structures, confirm the flow feasibility. The tested MP18 structures show a median line resistance of 720 Ω/µm and a clean line-to-line leakage with breakdown voltages in the range of 12-14V.

P4. Technology benchmarking of copper electromigration using a grain-sensitive simulation framework (Student Paper)

Ahmed S. Saleh, Kristof Croes, Hajdin Ceric, Ingrid De Wolf, Houman Zahedmanesh – IMEC

A calibrated simulation framework for the analysis of electromigration (EM) in nano-interconnects, incorporating the intricate influence of microstructure, is presented. Different technology options were benchmarked for EM performance, taking copper texture and microstructural changes with scaling into account. Specifically, the impacts of metal cap and copper doping were simulated for a constant line height of 80nm and for linewidths between 20 and 100nm. An almost linear increase in normalized lifetime was observed for aspect ratios of 1 and above. An increase ranging from 10x to 100x was gained by using a metal cap for aspect ratios below 2. However, its effectiveness strongly weakened with decreasing CD with almost no EM lifetime gain for 20nm CD. Doping elements that lower grain boundary diffusivity were found to be more effective at these small dimensions.

P5. Patterning process and electrical yield optimization at the limits of single exposure EUV 0.33 NA: a pitch 26nm damascene process

Victor M. Blanco Carballo, Kevin Vandersmissen, Bart de Wachter, Kathleen Nafus, Yannick Feurprier, Thiam arame, Alex Hsu, Cyrus Tabery, Jan Doise, Peter De Schepper – IMEC, TEL, ASML, Inpria

In this work we have developed a single layer short loop damascene process to evaluate and optimize patterning performance of pitch 26nm single exposure 0.33 NA EUV. An electrical readout of 1m long meanders and forks-forks is used to compare the different processes and evaluate the amount of resist defects leading to shorts or opens. For the best process a full wafer combo yield of 99.7% is achieved (edge excluded) equivalent to 12 defects/cm2

P6. Interconnect Delay Modeling of Critical Paths in Angstrom Nodes (Student Paper)

Francesco Dell’Atti, Anita Farokhnejad, Odysseas Zografos, Pieter Weckx, Julien Ryckaert, Paul Heremans – IMEC

This work provides a methodology to analyze and model critical path interconnections of physically implemented digital designs in Angstrom nodes. The Elmore delay computation is applied to the detailed interconnect topology to provide a block-level statistical assessment of dominant parameters such as wire and via resistance (R), as well as wire and pin capacitance (C), on interconnect performance. Our methodology can rapidly assess the impact of back-end-of-line (BEOL) materials, interconnect geometries, and scaling boosters on the interconnect delay of complex digital designs, enabling fast turn-around time for Design-Technology Co-optimization (DTCO) loops. The model predicts delays with 1.3 percent of maximum mean error, standard deviations below 3 percent, and 23x speedups compared to conventional Static-Timing-Analysis (STA) sensitivity analyses.

P7. Ion Beam Deposition of Low-Resistivity Tungsten and Molybdenum for Interconnect Applications

Rutvik Mehta, Yuejing (Crystal) Wang, Ashish Kulkarni, Robert Walko, Paul Turner, Frank Cerio, Robert Caldwell – Veeco Instruments, Inc.

Refractory metals like tungsten and molybdenum with favorable resistivity scaling effects are promising candidates for nanometer scale interconnects for memory and logic. Ion beam deposition with the highest sputter energy and fine-scale control of deposition energetics enables metal thin films with ideal microstructures. Tungsten and molybdenum thin films deposited by ion beam deposition on 300mm wafers show large grained fully (110)-aligned microstructures presaging low-resistivity independent of the underlying substrates. Unlike other deposition approaches which require additional inserted layers and show underlayer dependence, ion beam deposition achieves lower resistivity in the as-deposited state independent of the underlying substrate. Resistivity versus thickness curves of ion beam deposited tungsten and molybdenum films shows ultra-low resistivity in the as-deposited state with scaling effects qualitatively similar to that of corresponding epitaxial films. These results establish the application of ion beam deposition of refractory metals as a very promising approach towards low-resistivity interconnects for the next generation of integrated devices.

P8. Formation of Lateral-Type High-Tc Superconductor Josephson Junction by Helium Ion Microscopy

Shinichi Ogawa, Tetsuro Misawa, Kosuke Kurushima, Yuji Otsuka, Yukinori Moritta, Chiharu Urano – National Institute of Advanced Industrial Science and Technology, Toray Research Center, Inc.

This paper presents, for the first time, the results of investigating the dependence of ion dose and temperature on the formation of Josephson junctions via helium ion irradiation of YBa2Cu3O7-; high-temperature superconductor thin films. Helium ion microscopy technology was employed for the helium ion irradiation. Our observations reveal that the characteristics of Josephson junctions can be controlled by the dose of helium ions. Converging the helium ion beam to a diameter of 0.35 nm, with an acceleration voltage of 30 kV, and an irradiation dose in the order of 1E17/cm2, demonstrates the formation of excellent lateral-type thin film Josephson junctions.

P9. Selective Co ALD for Chiplet-to-Wafer and Wafer-to-Wafer Bonding (Student Paper)

Cheng Hsuan Kuo, Madison Manley, Dipayan Pal, Rohan Sahay, Ravi Kanjolia, Mansour Moinpour, Jacob Woodruff, Jeffrey Spiegelman, Muhannad Bakir, Andrew Kummel – UCSD, Georgia Institute of Technology, EMD Electronics, RASIRC

Cyclic clean treatment by using strong oxidant: HOOH and reductant: N2H4 ¬was developed for Cu cleaning which can be applied in the inverse hybrid metal bonding process. Compared to UHV anneal at higher temperature (415C), cyclic clean process is only performed at 340C with lower surface impurities. Also, highly selective Co ALD is deposited on metal Cu but not on SiO2 even after 1000 ALD cycles.

P10. Enhancement of electromigration performance of molybdenum nanowires by CoMo capping

Sijie Gu, Haijun Cheng, Chun-Feng Hu, Xin-Ping Qu Ping – Fudan University

The electromigration performance of the Mo nanowires with different capping layers is measured. Results show that the CoMo capped Mo nanowires show better electromigration performance than that of the ones capped with Si3N4 or SiO2. It is found that the CoMo capping layer can effectively protect the Mo film from oxidation as well as nitridation, which is the main reason for the improved EM performance of the Mo nanowires.

P11. Data Analytics to Identify Improved Low k Films

William Entley, Achtyl Jennifer, Robert Ridgeway – EMD Electronics

This paper investigates the development of as deposited dense low k films with high mechanical strength, crucial for advanced semiconductor manufacturing. Over 1100 unique low k films from seventeen precursors were deposited and analyzed, focusing on mechanical properties. The study used a Design of Experiments (DOE) approach to maximize mechanical strength of each precursor. Data analytics were used to analyze and sort the low k films to identify precursors that had the highest mechanical strength at a given value of the dielectric constant. This was done by extracting the Pareto Frontier, representing films with the highest mechanical strength at varying dielectric constants, for each precursor. Results showed significant variation in mechanical strength among precursors, with two novel precursors exhibiting superior performance compared to DMDMOS, an industry standard precursor. Analysis of the carbon distribution in the films provided insight into mechanical strength variations. This research highlights the potential of tailored precursor design to meet the demanding requirements of dense low k films in advanced semiconductor nodes.

P12. Halogen Free Low Temperature ALD Mo-based Films for Interconnects Applications

Aein Babadi, Randall Higuchi, Mike Savo, Charlene Chen, Bhushan Zope, Sergei Ivanov – EMD Electronics

Molybdenum-based films synthesized by low temperature atomic layer deposition (ALD) from different organometallic halogen free Molybdenum precursors. The film’s average composition was investigated and correlated with their nanoscale structures and electrical transport properties. A high work function N-rich MoN film with low carbon contamination was demonstrated in comparison with MoC/MoCN films with low resistivity. The precursor composition dependence of film’s properties leads to a low resistivity MoC film as well as selective deposition of Mo films on metallic substrates.

P13. Surface Characterization and Modification for Cu/SiCN Hybrid Bonding

Kenta Hayama, Kohei Nakayama, Ryosuke Sato, Yutetsu Kamiya, Ken Harada, Masahiro Yokoyama, Yasuhiro Kawase, Fumihiro Inoue – Yokohama National University, Mitsubishi Chemical Corporation

Hybrid bonding is an ideal bonding scheme for achieving finer interconnect pitch in multiple applications. To ensure high yielding, the pre-bonding surface preparation is a crucial process step as hybrid bonding requires surface uniformity of Cu pad. In this study, the influence of P-CMP cleaning and the effect of N2 plasma activation on Cu pad were investigated. The P-CMP alkaline cleaning solution can remove BTA residues. Furthermore, the plasma activation turns the Cu surface without any carbon related residues even with 15 sec process time. These results suggest an optimized surface condition for fine-pitch hybrid bonding.

 

P14. Low contact resistance copper-copper bonding with selective electroless plating cobalt interlayer

Yun-Hao Shao, Zihong Ni, Gui Chen, Hao Wang, Xin-Ping Qu – Fudan university

Low temperature metal direct bonding is very challenging in 3D interconnect technical. In this work, self aligned Co layer is selectively deposited on the copper line by electroless plating as an interlayer for Cu-Cu bonding. The direct bonding between Cu/Co is performed without a chemical mechanical polishing process at 250C; in ambient. An intact bonding interface is observed and a specific contact resistance of 5.5×10^-7 Ω·cm^2 is obtained. Through a special surface treatment, the specific contact resistance can achieve 3.8×10^-8 Ω·cm^2, which is lower than that of Cu-Cu bonding with PVD Co interlayer.

P15. Cyclic Etching of Mo Nanowires

Ivan Erofeev, Antony Winata Hartanto, Harold Philipsen, Antoine Pacco, Muhaimin Mareum Khan, Zainul Aabdin, Frank Holsteyns, Utkur Mirsaidov – National University of Singapore, IMEC

We show that a uniform recess of polycrystalline Mo films and nanowires can be achieved using a cyclical two-step method: isotropic oxygen plasma-based surface oxidation followed by selective etching of this oxide layer. The oxidation step fully defines the recess depth, and the low facet dependence of plasma oxidation ensures its uniformity. Our study describes the parameters (RF power, gas pressure, and exposure time) that affect and control the uniformity of oxidation of patterned Mo nanowires. We showed that using highly selective oxide etching, we can perform multiple etching cycles with a typical etch rate of 1-2 nm per cycle, depending on the RF power. Due to plasma isotropy, this approach can be implemented for a controlled uniform etching of large vertical stacks of metal nanostructures.

P16. Characterization of Siliconcarbonitride bonding layer for plasma activated direct fusion bonding

David Doppelbauer, Christoph Floetgen, Ignacio Gabriel Vicente Gabàs, Serena Iacovo, Steven Brems, Eric Beyne, Jiri Duchoslav, Heiko Groiss – EV Group E. Thallner GmbH, IMEC, Johannes Kepler University Linz

In the scope of this work, a comprehensive study of plasma treated Silicon carbonitride (SiCN) dielectric bonding surfaces on Si wafers is presented. PECVD grown films were investigated by means of variable angle spectroscopic ellipsometry (VASE) and angle-resolved x-ray photoelectron spectroscopy (ARXPS) before and after plasma activation. Based on ARXPS depth-profiling data, an ellipsometry model was developed, allowing for non-destructive characterization of the plasma effect on the SiCN bonding surfaces. Oxidation processes and intermediate mixture phase layers between the grown oxide and the SiCN layer were observed and correlated to plasma specific characteristics as measured by current-voltage probes. The plasma activation effect was further evaluated after bonding of SiCN wafer pairs in terms of bonding energy. Plasma characteristic parameters correlate well with oxide thickness after plasma activation and bonding energy.

P17. Investigation of the enlargement of Ru grains and failure modes analysis in microsecond UV laser annealing

Zeinab Chehadi, Richard Daubriac, Lu Lu, Karim Huet, Zsolt Tokei, Leonardo Cancellara, Fuccio Cristiano, Louis Thuries– LASSE-Screen, LAAS-CNRS, ScreenSPE, IMEC

Interconnects based on Ru has been considered as a promising candidate to replace Cu-based interconnects for the future technology nodes thanks to its low bulk resistivity , its short electron mean free path (e-MFP) and the possibility to have a barrier-less integration. In this work, we demonstrate that µs UV Laser Annealing (UV- LA) is an interesting process strategy to reduce the metal line resistance by enlarging grains in thin Ru films. A method based on numerical simulations has been proposed to optimize the LA conditions to lower the Ru film resistivity close to the bulk one, while avoiding the apparition of structural damages such as wrinkles or buckling.

P18. Nano-chemical characterization of SiO2 and Cu surfaces for Cu-Cu hybrid bonding

Padraic O’Reilly, Beihang Yu, Cheng Hsuan Kuo, Andrew Kummel, Ricardo Ruiz, Sung I. Park – Molecular Vista, Inc., Lawrence Berkeley National Laboratory, UCSD

Infrared photo-induced force microscopy (IR PiFM), which combines non-contact atomic force microscopy and infrared spectroscopy (AFM IR), is applied to precisely characterize the surface chemical state of the silicon oxide and copper. Based on an AFM platform, the technique can monitor the topographical condition (flatness of the dielectric as well as the recession of the Cu pads) in addition to the surface chemistry (absence of unwanted molecules and the presence of desired surface termination), both with ~ 5 nm lateral resolution and monolayer sensitivity, to characterize the suitability of the samples for successful Cu-Cu hybrid bonding.

P19. 300mm Wafer-scale ALD-grown MoS2 for Cu diffusion  barrier

Thong Ngo, Angelica Zacatzi, Yuanqiu Tan, Daniel Lee, Anand Wankis, Nguyen Vu, Ravi Kanjolia, Mansour Moinpour, Zhihong Chen – EMD Electronics, Purdue University

Cu has served as the interconnect metal in various chip generations, typically accompanied by a TaN/Ta diffusion barrier/liner. The size-scaling demand for future nodes requires thinning down TaN/Ta bi-layer. The thickness of TaN/Ta has reached the limit of its barrier/liner capability, necessitating the exploration of alternative diffusion barrier/liner materials. In this paper, we report the 300mm wafer-scale atomic layer deposited MoS2 as a promising candidate for Cu diffusion barrier/liner interconnect. MoS2 was deposited on thermal SiO2 substrate at the temperatures ranging from 200-550 °C. Good conformality of MoS2 was demonstrated on high aspect ratio structure. The resistivity of Cu/MoS2/SiO2 stack is lower than that of Cu/SiO2 stack. Time dependent dielectric breakdown of Cu/MoS2/SiO2 will be discussed and benchmarked with Cu/Ta/TaN/SiO2.

P20. Investigation of the Low Dielectric Constant Properties of SiOx/AlOx Nanolaminate Film (Student Paper)

Xinyu Wang, Jing Mu, James Huang, Yunil Cho, Kesong Wang, Dipayan Pal, Ajay Yadav, T. Wong Keith, Ellie Yieh, Srinivas Nemani, Andrew Kummel – UC San Diego, Applied Materials

Low-k materials play a pivotal role in semiconductor technologies, primarily due to their capability to enhance signal transmission speed and reduce power consumption. This study investigates a series of novel low-k (<2.5) SiOx/AlOx nanolaminate films with smooth surfaces deposited on Si substrates via a dual-temperature thermal chemical vapor deposition (CVD) process. The low dielectric constant value achieved by the nanolaminate is ascribed to its porous nature. Additionally, incorporating carbon into the nanolaminate structure greatly enhanced the atmospheric stability of the film by making it hydrophobic. P21. Enhanced process control for plasma triggered oxide growth in plasma activated wafer bonding

Christoph Floetgen, Ignacio Gabriel Vicente Gabàs, David Doppelbauer – EV Group E. Thallner GmbH

In Plasma Activated Wafer Bonding (PAWB) the plasma process modifies the surface conditions of a substrate, allowing for low-temperature annealing of the wafers to be bonded. Despite its critical role in the PAWB process, plasma treatment is often insufficiently characterized. In this study, electrical plasma parameters are recorded during the plasma activation process using current-voltage probes at the plasma chamber electrodes. These parameters are then correlated with bonding quality metrics like the plasma-triggered oxide growth on Si and the bond strength after annealing. As will be shown, particularly the oxide thickness grown after plasma activation can be determined by a simple functional correlation to plasma characteristic electrical parameters connected to the total dose of ions impinging on the wafer surface. This allows for potential enhanced process control, specifically in the light of the industry’s current and future challenges of shrinking device nodes.

P22. Metal-metal contact resistance measurements

Poyen Shen, Daniel Gall – Rensselaer Polytechnic Institute

The contact resistance at metal-metal (W, Mo, Ru, Co, TiN) interfaces is determined using a new method based on blanket superlattice thin films where the resistivity  parallel to the interfaces is measured as a function of superlattice period  to quantify the electron interface scattering. Epitaxial W(001)/Mo(001) superlattices show a continuous resistivity increase from 7.10 to 8.62 µΩ-cm with decreasing  = 50-1.7 nm, indicating a contact resistance of 2.6×10-16 Ω-m2. Ru/Co multilayers show a much more pronounced increase from 15.0 to 47.5 µΩ-cm with  = 60-2 nm which is attributed to atomic intermixing leading to an interfacial Ru-Co alloy with a high measured  = 61 µΩ-cm and a Ru-Co contact resistance for interfaces deposited at 400 °C of 9.1 ×10^-15 Ω-m2. Ru/TiN and Co/TiN interface resistances are dominated by the high for TiN, and are therefore proportional to the TiN thickness.

P23. Wafer-Level Electrochemical Deposition and Processing of Nanotwinned Cu RDL

Chih-Hao Hsia, SungHo Park, Soichi Watanabe, Marco Arnold, Zaid El-Mekki, Martine Delande, Ehsan Shafahian, Punith Kumar M. K. Gowda, Herbert Struyf, Aleksandar Radisic – BASF, IMEC

We have successfully performed wafer-level (300 mm) fabrication of highly (111) oriented nanotwinned copper (nt-Cu) Redistribution layers (RDL) using through-resist electrochemical deposition on barrier/seed combinations such as TiW/Cu, TaN/Cu, and TaN/Ta/Cu.    We have examined physical-chemical properties of nt-Cu and explored possible challenges in post-plating processing of these structures.  After photoresist removal, nt-Cu lines were analyzed using Scanning electron microscopy (SEM) and Focused ion beam (FIB) techniques.  Within wafer (WIW) and within die (WID) feature height uniformity were measured using profilometry and Cu losses in the plated lines upon wet-etch of the Cu seed were examined using automated SEM measurements.

 

P24. Mechanistic and Performance Aspects for Co-designed Process Technology to Enable Mo as the Next Generation Conductor

Michael White, Kevin Dockery, Paul Besser, Daniela White, Bryan Hendrix, Don Frye, Maryam Farmand, Jun Liu, Das Atanu, Jason Seabold, Fernando Hung – Entegris

PVD and CVD molybdenum (Mo) wafers/coupons were prepared and analyzed by various techniques including XPS, electrochemistry, impedance spectroscopy, AFM, Zeta Potential, Raman as well as ATR FTIR spectroscopies. The surface chemistry was then correlated with performance parameters such as the static etch and polishing rates/profile in addition to the defectivity after Planarcore® brush cleaning using with Entegris ML slurries and AG-Mo series PCMP cleaners.

P25. The investigation of Ar plasma treatment on the contact resistance between metal-metal by a simple metal bonding simulation approach

Gui Chen, Yun-Hao Shao, Xin-Ping Qu – Fudan University

Reducing the direct metal bonding temperature is a challenge for 3D metal bonding. We present a simple fabrication process using the two-step PVD Cu / Co on the PVD Co / Cu surface with a vacuum break followed by annealing to simulate the real metal-metal bonding. Based on this approach, without critical requirement of cleanliness of the bonding surface, the parameters which impacts the bonding temperature and interface specific contact resistance can be efficiently find out. In this work, we first used this approach to choose the correct Kevin structure to measure the low contact resistance, and then the effects of Argon plasma activation of the Co layer, which is used as an interlayer for Cu-Cu bonding, were investigated. It is found that the Ar plasma activation can result in uniform Co3O4 layer formation and effectively reduce contact resistance.

P26. Doping Effects in Grain Boundaries of Tungsten: Insights from First-Principle Study

Yeongjun Lim, Mincheol Shin – Korea Advanced Institute of Science and Technology

As semiconductor device sizes shrink to the nanometer scale, the sharp increase in resistance due to grain boundary and surface scattering poses uncertainties regarding the continued use of copper as an interconnect material. In pursuit of alternatives, tungsten has emerged, but its high resistance due to scattering remains a challenge. This study investigates the effects of grain boundary doping, a potential method for reducing resistance, through first-principle simulations combining density functional theory (DFT) and non-equilibrium Green’s function (NEGF) method. Our simulations reveal that grain boundary doping with certain impurities can effectively reduce resistivity in specific coincidence site lattice grain boundaries of tungsten interconnects.

P27. The feasibility of the lateral wet-etching on TiN layers in 3D multilayer stack structure

Jiao Jin, Jiabao Sun, tuo xin, Weidu Qin, Chaoyang Guan, wenjun chen, Chao Tian, Baodong Han, Hongbo Sun, Chao Zhao – Beijing Superstring Academy of Memory Technology

3D Memory Device is manufactured based on dielectric materials of SiOx and SiN vertically multilayer stacked semiconductor structures. Atomic Layer Deposition (ALD) have homogeneous step coverage of sidewalls and bottom with high aspect ratios in achieve 3D structure. But existing inherently void defect in lateral pocket layers. The worse uniformity and profile appeared after wet lateral etch along with pre-process layer seam, affecting seriously the storage properties of the device and lead to slower transfer speeds. In this study, Oxide Trim (wet isotropic etching SiOx) provides a new strategy for wet lateral etching TiN thin films by ALD technology of seam issue. The trumpet shaped opening between the stacked layers formed by twice lateral wet etching SiN promoted the seam inward after deposition, potential increasing the filler metal density in the seal and improving the BL uniformity using wet chemical of high etching selectivity for TiN to SiOx/SiN.

P28. Proposal for Improved Electrical Efficiency through Thermal Modeling of Interconnect Structure (Student Paper)

Taeyeong Hong, Seul Ki Hong – Seoul National University of Science & Technology

This study investigated the modeling of heat and current distribution in interconnect structure used in semiconductor systems based on their shapes, utilizing Finite Element Method (FEM) simulations. The research aims to optimize power efficiency in interconnect structures by securing the modeling of heat and current distribution through experimental validation, confirming the integrity of the models. In interconnect structures, the current density increases as the contact area for current flow at the junction of metal lines and vias narrows, leading to a temperature rise due to Joule heating. The need for scaling down exacerbates the issue as the dimensions need to be progressively reduced, conforming to the specifications of both lower and upper components, causing a reduction in the width of the conductors. The temperature increase due to Joule heating is inevitable with this reduced area, and it ultimately leads to the destruction, directly impacting the reliability of the entire system. The experimental results provide considerations for reliability when significantly scaling down interconnect structures in current semiconductor systems. Furthermore, these findings can be widely applied to research aimed at developing interconnect structures that enhance reliability.

P29. Lateral Metal Deposition and the Formation of Interconnection

Weidu Qin, Jiabao Sun, Jiao Jin, Chao Tian, Chaoyang Guan, Hongbo Sun, Chao Zhao – Beijing Superstring Academy of Memory Technology

With the development of semiconductor technology, the device architecture has developed from two-dimensional stacking to three-dimensional stacking, which makes it difficult to deposit interconnected metal films in multi-layer stacking structures. In order to obtain higher quality interconnection films, we used atomic layer deposition (ALD) and WET ETCH process to form TiN metal films in a multilayer stacked lateral structure. After WET ETCH, a straight profile was obtained and a seam-control TiN film was formed. This method shows good potential in depositing high-quality thin films and forming metal interconnections in multi-layer stacked devices.

P30. Thermally Conductivity Study of One Micron AlN Deposition by Bipolar High Power Impulse Magnetron Sputtering (Student Paper)

Ping Che Lee, Mcleod Aaron, Mingeun Choi, Vaca Diego, Satish Kumar, Andrew Kummel – UCSD, Georgia Institute of Technology

High Power Impulse Magnetron Sputtering (HIPIMS) has emerged as a promising technique for the deposition of thin films with superior properties. In this study, HIPIMS was combined with a positive target bias (Kick voltage) process to enhance AlN film quality further. Aluminum Nitride (AlN) thin films were deposited using this method and characterized using Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD). The thermal properties of the films were investigated using Frequency Domain Thermoreflectance (FDTR). The results show that the HIPIMS plus Kick process significantly improves the film quality, leading to enhanced thermal conductivity (112 W/ m·K) compared to conventional techniques. This work demonstrates the potential of HIPIMS in producing high-quality thin films with improved thermal properties, making it suitable for various applications in electronics and thermal management.